Hierarchical Hashing: A Dynamic Hashing Method with Low Write Amplification and High Performance for Non-Volatile Memory
The hashing method is widely used as the index structure, which can be stored in NVM to improve the application performance. However, existing hashing methods may cause high extra write amplification to NVM and bring high additional storage overhead on NVM, resulting in low request performance. To s...
Gespeichert in:
Veröffentlicht in: | IEEE transactions on computers 2024-12, p.1-14 |
---|---|
Hauptverfasser: | , , , , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 14 |
---|---|
container_issue | |
container_start_page | 1 |
container_title | IEEE transactions on computers |
container_volume | |
creator | Wang, Jinquan Huo, Zhisheng Xiao, Limin Yang, Jinqian Huo, Jiantong Guo, Minyi |
description | The hashing method is widely used as the index structure, which can be stored in NVM to improve the application performance. However, existing hashing methods may cause high extra write amplification to NVM and bring high additional storage overhead on NVM, resulting in low request performance. To solve these problems, we have proposed a dynamic hashing method called Hierarchical Hashing , whose basic idea is to leverage a novel hash collision resolution mechanism that can dynamically expand the size of the hash table. Hierarchical Hashing can incur no extra write amplification to NVM when resolving hash collisions. Additionally, it can directly address all cells when resizing the hash table, thereby avoiding the additional storage overhead caused by non-addressable linked lists. Furthermore, the request performance can be improved as all cells of the hash table are addressable when resizing to resolve hash collisions. The experimental results show that Hierarchical Hashing brings no extra write amplification to NVM and achieves nearly 90% space utilization and high request performance while providing 99% memory utilization, compared with existing representative hashing methods. |
doi_str_mv | 10.1109/TC.2024.3517737 |
format | Article |
fullrecord | <record><control><sourceid>ieee_RIE</sourceid><recordid>TN_cdi_ieee_primary_10803027</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>10803027</ieee_id><sourcerecordid>10803027</sourcerecordid><originalsourceid>FETCH-ieee_primary_108030273</originalsourceid><addsrcrecordid>eNqFjL1uwkAQhK8IUgikpkmxL2Cz54MYp0MkkQtAFFZSopNZcxvdDzpbIn77uAg11YzmmxkhZhJTKbGYV5s0w2yRqqXMc5U_iDGiXCWFWuCjeGrbH0R8zbAYi9-SKepYG661hVK3hv35Ddbw3nvtuL5FsKPOhBNcuTOwDVf4jtwRrN3FcjNsOw4etD9ByWcDB4pNiE77mmAwsA8--Qp2aFkanlyI_VSMGm1bev7XiXj5_Kg2ZcJEdLxEdjr2R4krVJjl6g7-A2fdS1c</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Hierarchical Hashing: A Dynamic Hashing Method with Low Write Amplification and High Performance for Non-Volatile Memory</title><source>IEEE Electronic Library (IEL)</source><creator>Wang, Jinquan ; Huo, Zhisheng ; Xiao, Limin ; Yang, Jinqian ; Huo, Jiantong ; Guo, Minyi</creator><creatorcontrib>Wang, Jinquan ; Huo, Zhisheng ; Xiao, Limin ; Yang, Jinqian ; Huo, Jiantong ; Guo, Minyi</creatorcontrib><description>The hashing method is widely used as the index structure, which can be stored in NVM to improve the application performance. However, existing hashing methods may cause high extra write amplification to NVM and bring high additional storage overhead on NVM, resulting in low request performance. To solve these problems, we have proposed a dynamic hashing method called Hierarchical Hashing , whose basic idea is to leverage a novel hash collision resolution mechanism that can dynamically expand the size of the hash table. Hierarchical Hashing can incur no extra write amplification to NVM when resolving hash collisions. Additionally, it can directly address all cells when resizing the hash table, thereby avoiding the additional storage overhead caused by non-addressable linked lists. Furthermore, the request performance can be improved as all cells of the hash table are addressable when resizing to resolve hash collisions. The experimental results show that Hierarchical Hashing brings no extra write amplification to NVM and achieves nearly 90% space utilization and high request performance while providing 99% memory utilization, compared with existing representative hashing methods.</description><identifier>ISSN: 0018-9340</identifier><identifier>DOI: 10.1109/TC.2024.3517737</identifier><identifier>CODEN: ITCOB4</identifier><language>eng</language><publisher>IEEE</publisher><subject>Computers ; Data structures ; Delays ; hash collision ; hashing method ; index structure ; Indexes ; Memory management ; Nonvolatile memory ; NVM ; Phase change materials ; Random access memory ; Resistance ; Time complexity ; write amplification</subject><ispartof>IEEE transactions on computers, 2024-12, p.1-14</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10803027$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10803027$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Wang, Jinquan</creatorcontrib><creatorcontrib>Huo, Zhisheng</creatorcontrib><creatorcontrib>Xiao, Limin</creatorcontrib><creatorcontrib>Yang, Jinqian</creatorcontrib><creatorcontrib>Huo, Jiantong</creatorcontrib><creatorcontrib>Guo, Minyi</creatorcontrib><title>Hierarchical Hashing: A Dynamic Hashing Method with Low Write Amplification and High Performance for Non-Volatile Memory</title><title>IEEE transactions on computers</title><addtitle>TC</addtitle><description>The hashing method is widely used as the index structure, which can be stored in NVM to improve the application performance. However, existing hashing methods may cause high extra write amplification to NVM and bring high additional storage overhead on NVM, resulting in low request performance. To solve these problems, we have proposed a dynamic hashing method called Hierarchical Hashing , whose basic idea is to leverage a novel hash collision resolution mechanism that can dynamically expand the size of the hash table. Hierarchical Hashing can incur no extra write amplification to NVM when resolving hash collisions. Additionally, it can directly address all cells when resizing the hash table, thereby avoiding the additional storage overhead caused by non-addressable linked lists. Furthermore, the request performance can be improved as all cells of the hash table are addressable when resizing to resolve hash collisions. The experimental results show that Hierarchical Hashing brings no extra write amplification to NVM and achieves nearly 90% space utilization and high request performance while providing 99% memory utilization, compared with existing representative hashing methods.</description><subject>Computers</subject><subject>Data structures</subject><subject>Delays</subject><subject>hash collision</subject><subject>hashing method</subject><subject>index structure</subject><subject>Indexes</subject><subject>Memory management</subject><subject>Nonvolatile memory</subject><subject>NVM</subject><subject>Phase change materials</subject><subject>Random access memory</subject><subject>Resistance</subject><subject>Time complexity</subject><subject>write amplification</subject><issn>0018-9340</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqFjL1uwkAQhK8IUgikpkmxL2Cz54MYp0MkkQtAFFZSopNZcxvdDzpbIn77uAg11YzmmxkhZhJTKbGYV5s0w2yRqqXMc5U_iDGiXCWFWuCjeGrbH0R8zbAYi9-SKepYG661hVK3hv35Ddbw3nvtuL5FsKPOhBNcuTOwDVf4jtwRrN3FcjNsOw4etD9ByWcDB4pNiE77mmAwsA8--Qp2aFkanlyI_VSMGm1bev7XiXj5_Kg2ZcJEdLxEdjr2R4krVJjl6g7-A2fdS1c</recordid><startdate>20241213</startdate><enddate>20241213</enddate><creator>Wang, Jinquan</creator><creator>Huo, Zhisheng</creator><creator>Xiao, Limin</creator><creator>Yang, Jinqian</creator><creator>Huo, Jiantong</creator><creator>Guo, Minyi</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope></search><sort><creationdate>20241213</creationdate><title>Hierarchical Hashing: A Dynamic Hashing Method with Low Write Amplification and High Performance for Non-Volatile Memory</title><author>Wang, Jinquan ; Huo, Zhisheng ; Xiao, Limin ; Yang, Jinqian ; Huo, Jiantong ; Guo, Minyi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_108030273</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Computers</topic><topic>Data structures</topic><topic>Delays</topic><topic>hash collision</topic><topic>hashing method</topic><topic>index structure</topic><topic>Indexes</topic><topic>Memory management</topic><topic>Nonvolatile memory</topic><topic>NVM</topic><topic>Phase change materials</topic><topic>Random access memory</topic><topic>Resistance</topic><topic>Time complexity</topic><topic>write amplification</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Wang, Jinquan</creatorcontrib><creatorcontrib>Huo, Zhisheng</creatorcontrib><creatorcontrib>Xiao, Limin</creatorcontrib><creatorcontrib>Yang, Jinqian</creatorcontrib><creatorcontrib>Huo, Jiantong</creatorcontrib><creatorcontrib>Guo, Minyi</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><jtitle>IEEE transactions on computers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Wang, Jinquan</au><au>Huo, Zhisheng</au><au>Xiao, Limin</au><au>Yang, Jinqian</au><au>Huo, Jiantong</au><au>Guo, Minyi</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Hierarchical Hashing: A Dynamic Hashing Method with Low Write Amplification and High Performance for Non-Volatile Memory</atitle><jtitle>IEEE transactions on computers</jtitle><stitle>TC</stitle><date>2024-12-13</date><risdate>2024</risdate><spage>1</spage><epage>14</epage><pages>1-14</pages><issn>0018-9340</issn><coden>ITCOB4</coden><abstract>The hashing method is widely used as the index structure, which can be stored in NVM to improve the application performance. However, existing hashing methods may cause high extra write amplification to NVM and bring high additional storage overhead on NVM, resulting in low request performance. To solve these problems, we have proposed a dynamic hashing method called Hierarchical Hashing , whose basic idea is to leverage a novel hash collision resolution mechanism that can dynamically expand the size of the hash table. Hierarchical Hashing can incur no extra write amplification to NVM when resolving hash collisions. Additionally, it can directly address all cells when resizing the hash table, thereby avoiding the additional storage overhead caused by non-addressable linked lists. Furthermore, the request performance can be improved as all cells of the hash table are addressable when resizing to resolve hash collisions. The experimental results show that Hierarchical Hashing brings no extra write amplification to NVM and achieves nearly 90% space utilization and high request performance while providing 99% memory utilization, compared with existing representative hashing methods.</abstract><pub>IEEE</pub><doi>10.1109/TC.2024.3517737</doi></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 0018-9340 |
ispartof | IEEE transactions on computers, 2024-12, p.1-14 |
issn | 0018-9340 |
language | eng |
recordid | cdi_ieee_primary_10803027 |
source | IEEE Electronic Library (IEL) |
subjects | Computers Data structures Delays hash collision hashing method index structure Indexes Memory management Nonvolatile memory NVM Phase change materials Random access memory Resistance Time complexity write amplification |
title | Hierarchical Hashing: A Dynamic Hashing Method with Low Write Amplification and High Performance for Non-Volatile Memory |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T11%3A27%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Hierarchical%20Hashing:%20A%20Dynamic%20Hashing%20Method%20with%20Low%20Write%20Amplification%20and%20High%20Performance%20for%20Non-Volatile%20Memory&rft.jtitle=IEEE%20transactions%20on%20computers&rft.au=Wang,%20Jinquan&rft.date=2024-12-13&rft.spage=1&rft.epage=14&rft.pages=1-14&rft.issn=0018-9340&rft.coden=ITCOB4&rft_id=info:doi/10.1109/TC.2024.3517737&rft_dat=%3Cieee_RIE%3E10803027%3C/ieee_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=10803027&rfr_iscdi=true |