Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection

Specifying channel-based asynchronous circuits in SystemVerilog is a promising alternative design paradigm to combine the advantages of asynchronous circuits and industrial EDA supports. However, communicating through channels can be error-prone, potentially introducing deadlocks that cannot be dete...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2024-11, p.1-1
Hauptverfasser:	Lu, Longlong, Pan, Minxue, Lu, Yifei, Li, Xuandong
Format:	Artikel
Sprache:	eng
Schlagworte:	Asynchronous Circuit Asynchronous circuits Circuits Deadlock Detection Design automation Integrated circuit modeling Locality Logic Model checking Monitoring Protocols System recovery Very large scale integration
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