CodePM: Parity-Based Crash Consistency for Log-Free Persistent Transactional Memory
Emerging persistent memory (PM) can provide large persistent capacity with performance comparable to DRAM in modern memory systems. Persistent transactional memory (PTM) needs to ensure data consistency after unexpected power loss or crashes. Therefore, crash consistency strategies such as persisten...
Gespeichert in:
Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2024-11, p.1-1 |
---|---|
Hauptverfasser: | , , , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 1 |
---|---|
container_issue | |
container_start_page | 1 |
container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
container_volume | |
creator | Xu, Guanglei Hu, Yuchong Feng, Dan He, Wenpeng Huang, Junyuan |
description | Emerging persistent memory (PM) can provide large persistent capacity with performance comparable to DRAM in modern memory systems. Persistent transactional memory (PTM) needs to ensure data consistency after unexpected power loss or crashes. Therefore, crash consistency strategies such as persistent logging are still required. However, the additional overhead introduced by these strategies, such as significant extra writes on PM, can lead to system performance degradation. In this paper, we propose CodePM, a fault-tolerant PM transactional library that utilizes parity-based crash consistency to remove logging overhead while guaranteeing the correct state of data. CodePM reuses the decoding capability of parity to detect and recover inconsistent objects. To ensure consistency without logs when updating, CodePM employs fine-grained memory fences to carefully align potential inconsistency with the repairability of parity. To detect inconsistency without logs when recovering, CodePM utilizes optimistic speculative scanning recovery by reusing checksum and parity, which supports instant recovery with transient degraded reliability. Moreover, we study the memory fence blocking effects and further augment CodePM with pipelined encoding and persistent writing to hide update latency. We implemented CodePM on Pangolin, the state-of-the-art parity-based PTM for fault-tolerance. Evaluation results with real-world workloads on Intel Optane DCPMM show that CodePM can achieve up to 3.4x higher throughput than Pangolin. |
doi_str_mv | 10.1109/TCAD.2024.3493014 |
format | Article |
fullrecord | <record><control><sourceid>crossref_RIE</sourceid><recordid>TN_cdi_ieee_primary_10745609</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>10745609</ieee_id><sourcerecordid>10_1109_TCAD_2024_3493014</sourcerecordid><originalsourceid>FETCH-LOGICAL-c639-d8daeafbad7f0167edaa8361772cca7a495fbc6a2b9974579699ef832c644cdb3</originalsourceid><addsrcrecordid>eNpNkLtOwzAUhi0EEuXyAEgMfgEXO3bsmK0ECkitqET26MQ-hqA2RnaWvD2t2oHpH_6b9BFyJ_hcCG4fmnrxPC94oeZSWcmFOiMzYaVhSpTinMx4YSrGueGX5CrnH75PlIWdkc86etysH-kGUj9O7AkyelonyN-0jkPu84iDm2iIia7iF1smRLrBdDRG2iQYMrixjwNs6Rp3MU035CLANuPtSa9Js3xp6je2-nh9rxcr5rS0zFceEEIH3gQutEEPUEktjCmcAwPKlqFzGorOWqNKY7W1GCpZOK2U8528JuI461LMOWFof1O_gzS1grcHKO0BSnuA0p6g7Dv3x06PiP_y-wPNrfwDIYFe3w</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>CodePM: Parity-Based Crash Consistency for Log-Free Persistent Transactional Memory</title><source>IEEE Electronic Library (IEL)</source><creator>Xu, Guanglei ; Hu, Yuchong ; Feng, Dan ; He, Wenpeng ; Huang, Junyuan</creator><creatorcontrib>Xu, Guanglei ; Hu, Yuchong ; Feng, Dan ; He, Wenpeng ; Huang, Junyuan</creatorcontrib><description>Emerging persistent memory (PM) can provide large persistent capacity with performance comparable to DRAM in modern memory systems. Persistent transactional memory (PTM) needs to ensure data consistency after unexpected power loss or crashes. Therefore, crash consistency strategies such as persistent logging are still required. However, the additional overhead introduced by these strategies, such as significant extra writes on PM, can lead to system performance degradation. In this paper, we propose CodePM, a fault-tolerant PM transactional library that utilizes parity-based crash consistency to remove logging overhead while guaranteeing the correct state of data. CodePM reuses the decoding capability of parity to detect and recover inconsistent objects. To ensure consistency without logs when updating, CodePM employs fine-grained memory fences to carefully align potential inconsistency with the repairability of parity. To detect inconsistency without logs when recovering, CodePM utilizes optimistic speculative scanning recovery by reusing checksum and parity, which supports instant recovery with transient degraded reliability. Moreover, we study the memory fence blocking effects and further augment CodePM with pipelined encoding and persistent writing to hide update latency. We implemented CodePM on Pangolin, the state-of-the-art parity-based PTM for fault-tolerance. Evaluation results with real-world workloads on Intel Optane DCPMM show that CodePM can achieve up to 3.4x higher throughput than Pangolin.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/TCAD.2024.3493014</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>IEEE</publisher><subject>Computer crashes ; Crash consistency ; Encoding ; erasure coding ; Fault tolerance ; Fault tolerant systems ; Hardware ; Media ; persistent memory (PM) ; Random access memory ; Software ; System performance ; Termination of employment</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 2024-11, p.1-1</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><orcidid>0009-0005-1415-1592 ; 0000-0002-4674-6006 ; 0000-0002-1165-8460 ; 0000-0003-1265-7141</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10745609$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10745609$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Xu, Guanglei</creatorcontrib><creatorcontrib>Hu, Yuchong</creatorcontrib><creatorcontrib>Feng, Dan</creatorcontrib><creatorcontrib>He, Wenpeng</creatorcontrib><creatorcontrib>Huang, Junyuan</creatorcontrib><title>CodePM: Parity-Based Crash Consistency for Log-Free Persistent Transactional Memory</title><title>IEEE transactions on computer-aided design of integrated circuits and systems</title><addtitle>TCAD</addtitle><description>Emerging persistent memory (PM) can provide large persistent capacity with performance comparable to DRAM in modern memory systems. Persistent transactional memory (PTM) needs to ensure data consistency after unexpected power loss or crashes. Therefore, crash consistency strategies such as persistent logging are still required. However, the additional overhead introduced by these strategies, such as significant extra writes on PM, can lead to system performance degradation. In this paper, we propose CodePM, a fault-tolerant PM transactional library that utilizes parity-based crash consistency to remove logging overhead while guaranteeing the correct state of data. CodePM reuses the decoding capability of parity to detect and recover inconsistent objects. To ensure consistency without logs when updating, CodePM employs fine-grained memory fences to carefully align potential inconsistency with the repairability of parity. To detect inconsistency without logs when recovering, CodePM utilizes optimistic speculative scanning recovery by reusing checksum and parity, which supports instant recovery with transient degraded reliability. Moreover, we study the memory fence blocking effects and further augment CodePM with pipelined encoding and persistent writing to hide update latency. We implemented CodePM on Pangolin, the state-of-the-art parity-based PTM for fault-tolerance. Evaluation results with real-world workloads on Intel Optane DCPMM show that CodePM can achieve up to 3.4x higher throughput than Pangolin.</description><subject>Computer crashes</subject><subject>Crash consistency</subject><subject>Encoding</subject><subject>erasure coding</subject><subject>Fault tolerance</subject><subject>Fault tolerant systems</subject><subject>Hardware</subject><subject>Media</subject><subject>persistent memory (PM)</subject><subject>Random access memory</subject><subject>Software</subject><subject>System performance</subject><subject>Termination of employment</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkLtOwzAUhi0EEuXyAEgMfgEXO3bsmK0ECkitqET26MQ-hqA2RnaWvD2t2oHpH_6b9BFyJ_hcCG4fmnrxPC94oeZSWcmFOiMzYaVhSpTinMx4YSrGueGX5CrnH75PlIWdkc86etysH-kGUj9O7AkyelonyN-0jkPu84iDm2iIia7iF1smRLrBdDRG2iQYMrixjwNs6Rp3MU035CLANuPtSa9Js3xp6je2-nh9rxcr5rS0zFceEEIH3gQutEEPUEktjCmcAwPKlqFzGorOWqNKY7W1GCpZOK2U8528JuI461LMOWFof1O_gzS1grcHKO0BSnuA0p6g7Dv3x06PiP_y-wPNrfwDIYFe3w</recordid><startdate>20241105</startdate><enddate>20241105</enddate><creator>Xu, Guanglei</creator><creator>Hu, Yuchong</creator><creator>Feng, Dan</creator><creator>He, Wenpeng</creator><creator>Huang, Junyuan</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><orcidid>https://orcid.org/0009-0005-1415-1592</orcidid><orcidid>https://orcid.org/0000-0002-4674-6006</orcidid><orcidid>https://orcid.org/0000-0002-1165-8460</orcidid><orcidid>https://orcid.org/0000-0003-1265-7141</orcidid></search><sort><creationdate>20241105</creationdate><title>CodePM: Parity-Based Crash Consistency for Log-Free Persistent Transactional Memory</title><author>Xu, Guanglei ; Hu, Yuchong ; Feng, Dan ; He, Wenpeng ; Huang, Junyuan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c639-d8daeafbad7f0167edaa8361772cca7a495fbc6a2b9974579699ef832c644cdb3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Computer crashes</topic><topic>Crash consistency</topic><topic>Encoding</topic><topic>erasure coding</topic><topic>Fault tolerance</topic><topic>Fault tolerant systems</topic><topic>Hardware</topic><topic>Media</topic><topic>persistent memory (PM)</topic><topic>Random access memory</topic><topic>Software</topic><topic>System performance</topic><topic>Termination of employment</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Xu, Guanglei</creatorcontrib><creatorcontrib>Hu, Yuchong</creatorcontrib><creatorcontrib>Feng, Dan</creatorcontrib><creatorcontrib>He, Wenpeng</creatorcontrib><creatorcontrib>Huang, Junyuan</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Xu, Guanglei</au><au>Hu, Yuchong</au><au>Feng, Dan</au><au>He, Wenpeng</au><au>Huang, Junyuan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>CodePM: Parity-Based Crash Consistency for Log-Free Persistent Transactional Memory</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>2024-11-05</date><risdate>2024</risdate><spage>1</spage><epage>1</epage><pages>1-1</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>Emerging persistent memory (PM) can provide large persistent capacity with performance comparable to DRAM in modern memory systems. Persistent transactional memory (PTM) needs to ensure data consistency after unexpected power loss or crashes. Therefore, crash consistency strategies such as persistent logging are still required. However, the additional overhead introduced by these strategies, such as significant extra writes on PM, can lead to system performance degradation. In this paper, we propose CodePM, a fault-tolerant PM transactional library that utilizes parity-based crash consistency to remove logging overhead while guaranteeing the correct state of data. CodePM reuses the decoding capability of parity to detect and recover inconsistent objects. To ensure consistency without logs when updating, CodePM employs fine-grained memory fences to carefully align potential inconsistency with the repairability of parity. To detect inconsistency without logs when recovering, CodePM utilizes optimistic speculative scanning recovery by reusing checksum and parity, which supports instant recovery with transient degraded reliability. Moreover, we study the memory fence blocking effects and further augment CodePM with pipelined encoding and persistent writing to hide update latency. We implemented CodePM on Pangolin, the state-of-the-art parity-based PTM for fault-tolerance. Evaluation results with real-world workloads on Intel Optane DCPMM show that CodePM can achieve up to 3.4x higher throughput than Pangolin.</abstract><pub>IEEE</pub><doi>10.1109/TCAD.2024.3493014</doi><tpages>1</tpages><orcidid>https://orcid.org/0009-0005-1415-1592</orcidid><orcidid>https://orcid.org/0000-0002-4674-6006</orcidid><orcidid>https://orcid.org/0000-0002-1165-8460</orcidid><orcidid>https://orcid.org/0000-0003-1265-7141</orcidid></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 0278-0070 |
ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 2024-11, p.1-1 |
issn | 0278-0070 1937-4151 |
language | eng |
recordid | cdi_ieee_primary_10745609 |
source | IEEE Electronic Library (IEL) |
subjects | Computer crashes Crash consistency Encoding erasure coding Fault tolerance Fault tolerant systems Hardware Media persistent memory (PM) Random access memory Software System performance Termination of employment |
title | CodePM: Parity-Based Crash Consistency for Log-Free Persistent Transactional Memory |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-10T19%3A46%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-crossref_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=CodePM:%20Parity-Based%20Crash%20Consistency%20for%20Log-Free%20Persistent%20Transactional%20Memory&rft.jtitle=IEEE%20transactions%20on%20computer-aided%20design%20of%20integrated%20circuits%20and%20systems&rft.au=Xu,%20Guanglei&rft.date=2024-11-05&rft.spage=1&rft.epage=1&rft.pages=1-1&rft.issn=0278-0070&rft.eissn=1937-4151&rft.coden=ITCSDI&rft_id=info:doi/10.1109/TCAD.2024.3493014&rft_dat=%3Ccrossref_RIE%3E10_1109_TCAD_2024_3493014%3C/crossref_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=10745609&rfr_iscdi=true |