Power Saving for Hardware Accelerated Applications with Dynamical Processor Switching

Services that require both heavy-load computation and low-latency have been increasing. To meet these requirements, an increasing number of servers are equipped with hardware accelerators such as a Graphics Processing Unit (GPU) or Field Programmable Gate Array (FPGA). These hardware accelerators ca...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	IEEE access 2024-01, Vol.12, p.1-1
Hauptverfasser:	Natori, Ko, Otani, Ikuo, Harasawa, Hikaru, Saito, Shogo, Fujimoto, Kei
Format:	Artikel
Sprache:	eng
Schlagworte:	Energy efficiency Field programmable gate arrays Field Programmable Gate Arrays (FPGAs) Graphics processing units Hardware acceleration Hardware Accelerator Low latency communication Middleware Power demand Servers Switches vRAN
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!