Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation
In this article, we describe an advanced multi-output fractional frequency synthesizer (FFS) featuring an innovative digital spur cancellation technique. This technique not only effectively suppresses fractional- N spurs but also eliminates externally coupled spurious tones. In addition, this artic...
Gespeichert in:
| Veröffentlicht in: | IEEE journal of solid-state circuits 2024-10, Vol.59 (10), p.3417-3431 |
|---|---|
| Hauptverfasser: | , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 3431 |
|---|---|
| container_issue | 10 |
| container_start_page | 3417 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 59 |
| creator | Zeinali, Mohammadreza Hung, Szu-Yao Pamarti, Sudhakar |
| description | In this article, we describe an advanced multi-output fractional frequency synthesizer (FFS) featuring an innovative digital spur cancellation technique. This technique not only effectively suppresses fractional- N spurs but also eliminates externally coupled spurious tones. In addition, this article includes a comprehensive exploration of the proposed method, offering theoretical analysis and simulation results to elucidate the associated design tradeoffs. Leveraging this novel spur cancellation approach, our synthesizer demonstrates exceptional performance, with results such as |
| doi_str_mv | 10.1109/JSSC.2024.3396799 |
| format | Article |
| fullrecord | <record><control><sourceid>crossref_RIE</sourceid><recordid>TN_cdi_ieee_primary_10531278</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>10531278</ieee_id><sourcerecordid>10_1109_JSSC_2024_3396799</sourcerecordid><originalsourceid>FETCH-LOGICAL-c148t-708a7295a6fbf867974d085fdd180fb15ce1a608dcff7c8f28064f80456b467e3</originalsourceid><addsrcrecordid>eNpNkE1OwzAQhS0EEqVwACQWvoDLOHFiR-qmpBSoKrFIK9hFrmO3RsEpcboIN-DWOCoLVvP73mg-hG4pTCiF7H5ZFPkkgohN4jhLeZadoRFNEkEoj9_P0QiACpJFAJfoyvuPUDIm6Aj9zLW3O4elq_DMybr31uPGYIkXrVSdbUIvpPrrqJ3qcdG7bh8U37rFb7bb42kGxHi8tF0XWoPLlFCISfWgcHE4trY5erxunPZ4463b4bnd2S54DkOcS6d0XcvhzjW6MLL2-uYvjtFm8bjOn8nq9ekln62Iokx0hIOQPMoSmZqtEeFTzioQiakqKsBsaaI0lSmIShnDlTCRgJQZASxJtyzlOh4jevJVbeN9q015aO2nbPuSQjmwLAeW5cCy_GMZNHcnjdVa_9tPYhpxEf8Cnbxw5A</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation</title><source>IEEE Electronic Library (IEL)</source><creator>Zeinali, Mohammadreza ; Hung, Szu-Yao ; Pamarti, Sudhakar</creator><creatorcontrib>Zeinali, Mohammadreza ; Hung, Szu-Yao ; Pamarti, Sudhakar</creatorcontrib><description><![CDATA[In this article, we describe an advanced multi-output fractional frequency synthesizer (FFS) featuring an innovative digital spur cancellation technique. This technique not only effectively suppresses fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula> spurs but also eliminates externally coupled spurious tones. In addition, this article includes a comprehensive exploration of the proposed method, offering theoretical analysis and simulation results to elucidate the associated design tradeoffs. Leveraging this novel spur cancellation approach, our synthesizer demonstrates exceptional performance, with results such as <90-fs integrated rms jitter and <inline-formula> <tex-math notation="LaTeX">\lt -103 </tex-math></inline-formula>-dBc spurious tones at a 2.48-GHz carrier frequency. A prototype IC with two FFSs, which can operate from 0.5 to 2.5 GHz, was fabricated in a 28-nm CMOS process to demonstrate the proposed spur cancellation technique. The digital core of FFS consumes 2.6 mW from 0.9-V supply with an area of 0.15 mm2.]]></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2024.3396799</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bang–bang phase detector (BBPD) ; Calibration ; Clocks ; delta-sigma modulation ; digital spur cancellation ; digital-to-phase converter (DPC) ; fractional frequency synthesizer (FFS) ; Frequency conversion ; Frequency synthesizers ; high-pass-shaped dithering ; Jitter ; phase interpolation ; Phase locked loops ; Phase noise</subject><ispartof>IEEE journal of solid-state circuits, 2024-10, Vol.59 (10), p.3417-3431</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c148t-708a7295a6fbf867974d085fdd180fb15ce1a608dcff7c8f28064f80456b467e3</cites><orcidid>0009-0002-8233-1198 ; 0000-0003-1457-7508</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10531278$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27923,27924,54757</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10531278$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Zeinali, Mohammadreza</creatorcontrib><creatorcontrib>Hung, Szu-Yao</creatorcontrib><creatorcontrib>Pamarti, Sudhakar</creatorcontrib><title>Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description><![CDATA[In this article, we describe an advanced multi-output fractional frequency synthesizer (FFS) featuring an innovative digital spur cancellation technique. This technique not only effectively suppresses fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula> spurs but also eliminates externally coupled spurious tones. In addition, this article includes a comprehensive exploration of the proposed method, offering theoretical analysis and simulation results to elucidate the associated design tradeoffs. Leveraging this novel spur cancellation approach, our synthesizer demonstrates exceptional performance, with results such as <90-fs integrated rms jitter and <inline-formula> <tex-math notation="LaTeX">\lt -103 </tex-math></inline-formula>-dBc spurious tones at a 2.48-GHz carrier frequency. A prototype IC with two FFSs, which can operate from 0.5 to 2.5 GHz, was fabricated in a 28-nm CMOS process to demonstrate the proposed spur cancellation technique. The digital core of FFS consumes 2.6 mW from 0.9-V supply with an area of 0.15 mm2.]]></description><subject>Bang–bang phase detector (BBPD)</subject><subject>Calibration</subject><subject>Clocks</subject><subject>delta-sigma modulation</subject><subject>digital spur cancellation</subject><subject>digital-to-phase converter (DPC)</subject><subject>fractional frequency synthesizer (FFS)</subject><subject>Frequency conversion</subject><subject>Frequency synthesizers</subject><subject>high-pass-shaped dithering</subject><subject>Jitter</subject><subject>phase interpolation</subject><subject>Phase locked loops</subject><subject>Phase noise</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkE1OwzAQhS0EEqVwACQWvoDLOHFiR-qmpBSoKrFIK9hFrmO3RsEpcboIN-DWOCoLVvP73mg-hG4pTCiF7H5ZFPkkgohN4jhLeZadoRFNEkEoj9_P0QiACpJFAJfoyvuPUDIm6Aj9zLW3O4elq_DMybr31uPGYIkXrVSdbUIvpPrrqJ3qcdG7bh8U37rFb7bb42kGxHi8tF0XWoPLlFCISfWgcHE4trY5erxunPZ4463b4bnd2S54DkOcS6d0XcvhzjW6MLL2-uYvjtFm8bjOn8nq9ekln62Iokx0hIOQPMoSmZqtEeFTzioQiakqKsBsaaI0lSmIShnDlTCRgJQZASxJtyzlOh4jevJVbeN9q015aO2nbPuSQjmwLAeW5cCy_GMZNHcnjdVa_9tPYhpxEf8Cnbxw5A</recordid><startdate>202410</startdate><enddate>202410</enddate><creator>Zeinali, Mohammadreza</creator><creator>Hung, Szu-Yao</creator><creator>Pamarti, Sudhakar</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><orcidid>https://orcid.org/0009-0002-8233-1198</orcidid><orcidid>https://orcid.org/0000-0003-1457-7508</orcidid></search><sort><creationdate>202410</creationdate><title>Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation</title><author>Zeinali, Mohammadreza ; Hung, Szu-Yao ; Pamarti, Sudhakar</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c148t-708a7295a6fbf867974d085fdd180fb15ce1a608dcff7c8f28064f80456b467e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Bang–bang phase detector (BBPD)</topic><topic>Calibration</topic><topic>Clocks</topic><topic>delta-sigma modulation</topic><topic>digital spur cancellation</topic><topic>digital-to-phase converter (DPC)</topic><topic>fractional frequency synthesizer (FFS)</topic><topic>Frequency conversion</topic><topic>Frequency synthesizers</topic><topic>high-pass-shaped dithering</topic><topic>Jitter</topic><topic>phase interpolation</topic><topic>Phase locked loops</topic><topic>Phase noise</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Zeinali, Mohammadreza</creatorcontrib><creatorcontrib>Hung, Szu-Yao</creatorcontrib><creatorcontrib>Pamarti, Sudhakar</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zeinali, Mohammadreza</au><au>Hung, Szu-Yao</au><au>Pamarti, Sudhakar</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2024-10</date><risdate>2024</risdate><volume>59</volume><issue>10</issue><spage>3417</spage><epage>3431</epage><pages>3417-3431</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract><![CDATA[In this article, we describe an advanced multi-output fractional frequency synthesizer (FFS) featuring an innovative digital spur cancellation technique. This technique not only effectively suppresses fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula> spurs but also eliminates externally coupled spurious tones. In addition, this article includes a comprehensive exploration of the proposed method, offering theoretical analysis and simulation results to elucidate the associated design tradeoffs. Leveraging this novel spur cancellation approach, our synthesizer demonstrates exceptional performance, with results such as <90-fs integrated rms jitter and <inline-formula> <tex-math notation="LaTeX">\lt -103 </tex-math></inline-formula>-dBc spurious tones at a 2.48-GHz carrier frequency. A prototype IC with two FFSs, which can operate from 0.5 to 2.5 GHz, was fabricated in a 28-nm CMOS process to demonstrate the proposed spur cancellation technique. The digital core of FFS consumes 2.6 mW from 0.9-V supply with an area of 0.15 mm2.]]></abstract><pub>IEEE</pub><doi>10.1109/JSSC.2024.3396799</doi><tpages>15</tpages><orcidid>https://orcid.org/0009-0002-8233-1198</orcidid><orcidid>https://orcid.org/0000-0003-1457-7508</orcidid></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2024-10, Vol.59 (10), p.3417-3431 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_ieee_primary_10531278 |
| source | IEEE Electronic Library (IEL) |
| subjects | Bang–bang phase detector (BBPD) Calibration Clocks delta-sigma modulation digital spur cancellation digital-to-phase converter (DPC) fractional frequency synthesizer (FFS) Frequency conversion Frequency synthesizers high-pass-shaped dithering Jitter phase interpolation Phase locked loops Phase noise |
| title | Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T11%3A38%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-crossref_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Design%20and%20Analysis%20of%20a%20Fractional%20Frequency%20Synthesizer%20With%20%3C90-fs%20Jitter%20and%20%3C-103-dBc%20Spurious%20Tones%20Using%20Digital%20Spur%20Cancellation&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Zeinali,%20Mohammadreza&rft.date=2024-10&rft.volume=59&rft.issue=10&rft.spage=3417&rft.epage=3431&rft.pages=3417-3431&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.2024.3396799&rft_dat=%3Ccrossref_RIE%3E10_1109_JSSC_2024_3396799%3C/crossref_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=10531278&rfr_iscdi=true |