Improved Parasitic Capacitance-Predictively Aware DTCO: Enhanced Cell Efficiency With Manufacturability and Scalability for 4F2 VCT-Based DRAM

The 4F2 cell architecture dynamic random access memory (DRAM) has emerged as a candidate for high-density future DRAM, meeting performance, power, area, and cost (PPAC) targets. This study proposes an improved parasitic capacitance-predictively aware design technology co-optimization (DTCO) flow tha...

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Veröffentlicht in:	IEEE transactions on electron devices 2024-07, Vol.71 (7), p.4132-4137
Hauptverfasser:	Liang, Honggang, Yu, Yong, Li, Zhixuan, Li, Yuke, Shao, Feng, Zhu, Jingfei, Lu, Yanan, Liang, Jing, Ba, Lansong, Yang, Nan, Li, Yongjie, Peng, Xu, Lu, Yongchun, Kang, Bryan, Wang, Guilei, Zhao, Chao
Format:	Artikel
Sprache:	eng
Schlagworte:	Air gap and cost (PPAC) area Arrays bitline (BL) BL capacitance (CBL) Capacitance Computer architecture Couplings Design optimization design technology co-optimization (DTCO) Dynamic random access memory dynamic random access memory (DRAM) Manufacturability Microprocessors parasitic extraction Parasitics (electronics) power Power consumption Power management Random access memory read speed Scalability Transistors vertical channel transistor (VCT)
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