A 16 384-bit dynamic RAM

A 16 384-bit dynamic RAM

A 16-kbit dynamic RAM is described which is TTL compatible on all pins, and fits a standard 16-pin package. A single-transistor storage cell is used which occupies 455 /spl mu/m/SUP 2/. The device is fabricated in n-channel two-layer polysilicon gate technology using conventional design rules. The c...

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Veröffentlicht in:IEEE journal of solid-state circuits 1976-10, Vol.11 (5), p.570-574
Hauptverfasser: Ahlquist, C.N., Breivogel, J.R., Koo, J.T., McCollum, J.L., Oldham, W.G., Renninger, A.L.
Format: Artikel
Sprache:eng
Schlagworte:
Circuits
Clocks
Content addressable storage
DRAM chips
Packaging
Pins
Random access memory
Read-write memory
Silicon
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container_end_page 574
container_issue 5
container_start_page 570
container_title IEEE journal of solid-state circuits
container_volume 11
creator Ahlquist, C.N.
Breivogel, J.R.
Koo, J.T.
McCollum, J.L.
Oldham, W.G.
Renninger, A.L.
description A 16-kbit dynamic RAM is described which is TTL compatible on all pins, and fits a standard 16-pin package. A single-transistor storage cell is used which occupies 455 /spl mu/m/SUP 2/. The device is fabricated in n-channel two-layer polysilicon gate technology using conventional design rules. The chip size is 145 by 234 mils. A low-power sense amplifier is used for each 64 memory cells. A special refresh mode is possible in which all 256 sense amplifiers are active, and the entire memory can be refreshed in 64 address cycles.
doi_str_mv 10.1109/JSSC.1976.1050783
format Article
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ispartof IEEE journal of solid-state circuits, 1976-10, Vol.11 (5), p.570-574
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source IEEE Electronic Library (IEL)
subjects Circuits
Clocks
Content addressable storage
DRAM chips
Packaging
Pins
Random access memory
Read-write memory
Silicon
title A 16 384-bit dynamic RAM
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