Pin-Opt: Graph Representation Learning for Large-Scale Pin Assignment Optimization of Microbumps Considering Signal and Power Integrity
In this work, we propose a deep reinforcement learning (DRL) framework called Pin-opt, designed to create a reusable solver capable of optimizing pin assignment to minimize signal integrity (SI) and power integrity (PI) degradation in microbump packages. The increasing data rates of high-bandwidth s...
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creator | Park, Joonsang Choi, Seonguk Son, Keeyoung Lee, Junghyun Shin, Taein Kim, Keunwoo Sim, Boogyo Kim, Seongguk Kim, Jihun Yoon, Jiwon Kim, Youngwoo Kim, Joungho |
description | In this work, we propose a deep reinforcement learning (DRL) framework called Pin-opt, designed to create a reusable solver capable of optimizing pin assignment to minimize signal integrity (SI) and power integrity (PI) degradation in microbump packages. The increasing data rates of high-bandwidth systems have made SI/PI issues critical for ensuring the reliability of these systems. While previous research using meta-heuristic methods has optimized pin assignment to reduce SI/PI degradation in similar vertical interconnections, these approaches tend to be inflexible, providing problem-specific solutions suitable only for square-shaped pin arrangements. Our approach, Pin-opt, leverages the advantages of a learning-based method to create a practical solution applicable to pin maps of any shape and with a very large pin count. By representing pins as graphs during the training process, Pin-opt becomes adaptable to any pin arrangement and demonstrates significant performance improvements when solving large-scale pin assignment problems. We evaluate the performance, computational cost, reusability, and scalability of Pin-opt by comparing it to the genetic algorithm (GA), a conventional meta-heuristic method used for solving optimization tasks. To demonstrate its practicality, Pin-opt is also applied to a pin map of high bandwidth memory (HBM). |
doi_str_mv | 10.1109/TCPMT.2024.3381342 |
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The increasing data rates of high-bandwidth systems have made SI/PI issues critical for ensuring the reliability of these systems. While previous research using meta-heuristic methods has optimized pin assignment to reduce SI/PI degradation in similar vertical interconnections, these approaches tend to be inflexible, providing problem-specific solutions suitable only for square-shaped pin arrangements. Our approach, Pin-opt, leverages the advantages of a learning-based method to create a practical solution applicable to pin maps of any shape and with a very large pin count. By representing pins as graphs during the training process, Pin-opt becomes adaptable to any pin arrangement and demonstrates significant performance improvements when solving large-scale pin assignment problems. We evaluate the performance, computational cost, reusability, and scalability of Pin-opt by comparing it to the genetic algorithm (GA), a conventional meta-heuristic method used for solving optimization tasks. To demonstrate its practicality, Pin-opt is also applied to a pin map of high bandwidth memory (HBM).</description><identifier>ISSN: 2156-3950</identifier><identifier>EISSN: 2156-3985</identifier><identifier>DOI: 10.1109/TCPMT.2024.3381342</identifier><identifier>CODEN: ITCPC8</identifier><language>eng</language><publisher>Piscataway: IEEE</publisher><subject>Computational efficiency ; Deep learning ; Deep reinforcement learning ; Deep reinforcement learning (DRL) ; Degradation ; Genetic algorithms ; graph representation learning ; Graph representations ; Graphical representations ; Heuristic methods ; Machine learning ; Manufacturing ; Metaheuristics ; Optimization ; Packaging ; Performance evaluation ; pin assignment ; power integrity (PI) ; Representation learning ; Signal integrity ; signal integrity (SI) ; System reliability ; Training</subject><ispartof>IEEE transactions on components, packaging, and manufacturing technology (2011), 2024-04, Vol.14 (4), p.681-692</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2024</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c247t-f965082720f9d12a894932ca3d49999ba8e63110c890d2661ee1cc66795af74e3</cites><orcidid>0000-0003-1083-0385 ; 0000-0003-4269-7005 ; 0000-0002-8925-2604 ; 0000-0003-0096-2296 ; 0000-0001-5147-3076 ; 0000-0001-7003-5207 ; 0000-0003-1376-0781 ; 0000-0003-3019-3678 ; 0009-0001-5055-8905 ; 0000-0003-1040-4458 ; 0000-0001-6399-4995</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10478710$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10478710$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Park, Joonsang</creatorcontrib><creatorcontrib>Choi, Seonguk</creatorcontrib><creatorcontrib>Son, Keeyoung</creatorcontrib><creatorcontrib>Lee, Junghyun</creatorcontrib><creatorcontrib>Shin, Taein</creatorcontrib><creatorcontrib>Kim, Keunwoo</creatorcontrib><creatorcontrib>Sim, Boogyo</creatorcontrib><creatorcontrib>Kim, Seongguk</creatorcontrib><creatorcontrib>Kim, Jihun</creatorcontrib><creatorcontrib>Yoon, Jiwon</creatorcontrib><creatorcontrib>Kim, Youngwoo</creatorcontrib><creatorcontrib>Kim, Joungho</creatorcontrib><title>Pin-Opt: Graph Representation Learning for Large-Scale Pin Assignment Optimization of Microbumps Considering Signal and Power Integrity</title><title>IEEE transactions on components, packaging, and manufacturing technology (2011)</title><addtitle>TCPMT</addtitle><description>In this work, we propose a deep reinforcement learning (DRL) framework called Pin-opt, designed to create a reusable solver capable of optimizing pin assignment to minimize signal integrity (SI) and power integrity (PI) degradation in microbump packages. The increasing data rates of high-bandwidth systems have made SI/PI issues critical for ensuring the reliability of these systems. While previous research using meta-heuristic methods has optimized pin assignment to reduce SI/PI degradation in similar vertical interconnections, these approaches tend to be inflexible, providing problem-specific solutions suitable only for square-shaped pin arrangements. Our approach, Pin-opt, leverages the advantages of a learning-based method to create a practical solution applicable to pin maps of any shape and with a very large pin count. By representing pins as graphs during the training process, Pin-opt becomes adaptable to any pin arrangement and demonstrates significant performance improvements when solving large-scale pin assignment problems. We evaluate the performance, computational cost, reusability, and scalability of Pin-opt by comparing it to the genetic algorithm (GA), a conventional meta-heuristic method used for solving optimization tasks. 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We evaluate the performance, computational cost, reusability, and scalability of Pin-opt by comparing it to the genetic algorithm (GA), a conventional meta-heuristic method used for solving optimization tasks. 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subjects | Computational efficiency Deep learning Deep reinforcement learning Deep reinforcement learning (DRL) Degradation Genetic algorithms graph representation learning Graph representations Graphical representations Heuristic methods Machine learning Manufacturing Metaheuristics Optimization Packaging Performance evaluation pin assignment power integrity (PI) Representation learning Signal integrity signal integrity (SI) System reliability Training |
title | Pin-Opt: Graph Representation Learning for Large-Scale Pin Assignment Optimization of Microbumps Considering Signal and Power Integrity |
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