A 187-dB FoMS Power-Efficient Second-Order Highpass ΔΣ Capacitance-to-Digital Converter
The escalating demand for high-resolution sensor interface systems, driven by the proliferation of the Internet of Things (IoT) and wearable smart devices, has led to the widespread use of capacitive sensing transducers. These transducers are valued for their low-noise and low-power characteristics,...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2024-04, Vol.59 (4), p.1204-1215 |
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| container_title | IEEE journal of solid-state circuits |
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| creator | Jung, Yoontae Oh, Sein Ha, Sohmyung Je, Minkyu |
| description | The escalating demand for high-resolution sensor interface systems, driven by the proliferation of the Internet of Things (IoT) and wearable smart devices, has led to the widespread use of capacitive sensing transducers. These transducers are valued for their low-noise and low-power characteristics, making them suitable for various applications, including environmental and biomedical sensing. However, designing a high-resolution capacitive sensor interface system while maintaining power efficiency remains challenging. This article proposes a high-resolution energy-efficient highpass (HP) \Delta \Sigma capacitance-to-digital converter (CDC) architecture. The architecture incorporates a 2nd-order HP \Delta \Sigma modulator ( \Delta \Sigma \text{M} ) and a continuous-time capacitance-to-voltage converter (CT CVC). The proposed CDC achieves an excellent capacitance resolution of 5.85 aFrms, with a power efficiency of 46 fJ/conversion-step and an FoMS of 187.4 dB. The HP \Delta \Sigma \text{M} , designed with superior power efficiency, offers a promising solution for high-resolution capacitive sensor applications. Compared to state-of-the-art, the proposed CDC achieves more than 2 \times FoMS improvement while maintaining competitive FoMW. |
| doi_str_mv | 10.1109/JSSC.2024.3353008 |
| format | Article |
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These transducers are valued for their low-noise and low-power characteristics, making them suitable for various applications, including environmental and biomedical sensing. However, designing a high-resolution capacitive sensor interface system while maintaining power efficiency remains challenging. This article proposes a high-resolution energy-efficient highpass (HP) <inline-formula> <tex-math notation="LaTeX">\Delta \Sigma </tex-math></inline-formula> capacitance-to-digital converter (CDC) architecture. The architecture incorporates a 2nd-order HP <inline-formula> <tex-math notation="LaTeX">\Delta \Sigma </tex-math></inline-formula> modulator (<inline-formula> <tex-math notation="LaTeX">\Delta \Sigma \text{M} </tex-math></inline-formula>) and a continuous-time capacitance-to-voltage converter (CT CVC). The proposed CDC achieves an excellent capacitance resolution of 5.85 aFrms, with a power efficiency of 46 fJ/conversion-step and an FoMS of 187.4 dB. The HP <inline-formula> <tex-math notation="LaTeX">\Delta \Sigma \text{M} </tex-math></inline-formula>, designed with superior power efficiency, offers a promising solution for high-resolution capacitive sensor applications. Compared to state-of-the-art, the proposed CDC achieves more than 2<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> FoMS improvement while maintaining competitive FoMW.]]></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2024.3353008</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Capacitance ; capacitance-to-digital converter (CDC) ; Capacitive sensors ; Efficiency ; Harmonic analysis ; High resolution ; highpass (HP) ΔΣ CDC ; highpass ΔΣM ; Integrated circuits ; Internet of Things ; Internet of Things (IoT) ; Power harmonic filters ; Power management ; sensor interface integrated circuit (IC) ; Sensors ; Topology ; Transducers ; Voltage converters ; ΔΣ modulator (ΔΣM)</subject><ispartof>IEEE journal of solid-state circuits, 2024-04, Vol.59 (4), p.1204-1215</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2024</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><orcidid>0000-0002-1540-5102 ; 0000-0003-3589-086X ; 0000-0003-0461-6729 ; 0000-0003-4580-2771</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10414451$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10414451$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jung, Yoontae</creatorcontrib><creatorcontrib>Oh, Sein</creatorcontrib><creatorcontrib>Ha, Sohmyung</creatorcontrib><creatorcontrib>Je, Minkyu</creatorcontrib><title>A 187-dB FoMS Power-Efficient Second-Order Highpass ΔΣ Capacitance-to-Digital Converter</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description><![CDATA[The escalating demand for high-resolution sensor interface systems, driven by the proliferation of the Internet of Things (IoT) and wearable smart devices, has led to the widespread use of capacitive sensing transducers. These transducers are valued for their low-noise and low-power characteristics, making them suitable for various applications, including environmental and biomedical sensing. However, designing a high-resolution capacitive sensor interface system while maintaining power efficiency remains challenging. This article proposes a high-resolution energy-efficient highpass (HP) <inline-formula> <tex-math notation="LaTeX">\Delta \Sigma </tex-math></inline-formula> capacitance-to-digital converter (CDC) architecture. The architecture incorporates a 2nd-order HP <inline-formula> <tex-math notation="LaTeX">\Delta \Sigma </tex-math></inline-formula> modulator (<inline-formula> <tex-math notation="LaTeX">\Delta \Sigma \text{M} </tex-math></inline-formula>) and a continuous-time capacitance-to-voltage converter (CT CVC). The proposed CDC achieves an excellent capacitance resolution of 5.85 aFrms, with a power efficiency of 46 fJ/conversion-step and an FoMS of 187.4 dB. The HP <inline-formula> <tex-math notation="LaTeX">\Delta \Sigma \text{M} </tex-math></inline-formula>, designed with superior power efficiency, offers a promising solution for high-resolution capacitive sensor applications. Compared to state-of-the-art, the proposed CDC achieves more than 2<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> FoMS improvement while maintaining competitive FoMW.]]></description><subject>Capacitance</subject><subject>capacitance-to-digital converter (CDC)</subject><subject>Capacitive sensors</subject><subject>Efficiency</subject><subject>Harmonic analysis</subject><subject>High resolution</subject><subject>highpass (HP) ΔΣ CDC</subject><subject>highpass ΔΣM</subject><subject>Integrated circuits</subject><subject>Internet of Things</subject><subject>Internet of Things (IoT)</subject><subject>Power harmonic filters</subject><subject>Power management</subject><subject>sensor interface integrated circuit (IC)</subject><subject>Sensors</subject><subject>Topology</subject><subject>Transducers</subject><subject>Voltage converters</subject><subject>ΔΣ modulator (ΔΣM)</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNotkMFKw0AYhBdRsFYfQPCw4Hnr_-9uks2xxtYqlQpR0FPYJn_qlprETar4Hr6B79NnMlBPwwfDzDCMnSOMECG-uk_TZCRB6pFSgQIwB2yAQWAERurlkA0A0IhYAhyzk7Zd96i1wQF7HXM0kSiu-bR-SPlj_UVeTMrS5Y6qjqeU11UhFr4gz2du9dbYtuW7n90vT2xjc9fZKifR1eLGrXrY8KSuPsl35E_ZUWk3LZ3965A9TydPyUzMF7d3yXgunATdCRX28yE2eaGX1kShipaktURVSMoxR1ShDsvSoLQEEIXLMiywAIuBIhOaSA3Z5T638fXHltouW9dbX_WVmYzjALUEA73rYu9yRJQ13r1b_50h6P6HANUfBkpcIw</recordid><startdate>20240401</startdate><enddate>20240401</enddate><creator>Jung, Yoontae</creator><creator>Oh, Sein</creator><creator>Ha, Sohmyung</creator><creator>Je, Minkyu</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-1540-5102</orcidid><orcidid>https://orcid.org/0000-0003-3589-086X</orcidid><orcidid>https://orcid.org/0000-0003-0461-6729</orcidid><orcidid>https://orcid.org/0000-0003-4580-2771</orcidid></search><sort><creationdate>20240401</creationdate><title>A 187-dB FoMS Power-Efficient Second-Order Highpass ΔΣ Capacitance-to-Digital Converter</title><author>Jung, Yoontae ; Oh, Sein ; Ha, Sohmyung ; Je, Minkyu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i204t-36109098cd4ba87637be44213d2ec1c113646ff812ae0076bf6d1d0a153e86873</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Capacitance</topic><topic>capacitance-to-digital converter (CDC)</topic><topic>Capacitive sensors</topic><topic>Efficiency</topic><topic>Harmonic analysis</topic><topic>High resolution</topic><topic>highpass (HP) ΔΣ CDC</topic><topic>highpass ΔΣM</topic><topic>Integrated circuits</topic><topic>Internet of Things</topic><topic>Internet of Things (IoT)</topic><topic>Power harmonic filters</topic><topic>Power management</topic><topic>sensor interface integrated circuit (IC)</topic><topic>Sensors</topic><topic>Topology</topic><topic>Transducers</topic><topic>Voltage converters</topic><topic>ΔΣ modulator (ΔΣM)</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Jung, Yoontae</creatorcontrib><creatorcontrib>Oh, Sein</creatorcontrib><creatorcontrib>Ha, Sohmyung</creatorcontrib><creatorcontrib>Je, Minkyu</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jung, Yoontae</au><au>Oh, Sein</au><au>Ha, Sohmyung</au><au>Je, Minkyu</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 187-dB FoMS Power-Efficient Second-Order Highpass ΔΣ Capacitance-to-Digital Converter</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2024-04-01</date><risdate>2024</risdate><volume>59</volume><issue>4</issue><spage>1204</spage><epage>1215</epage><pages>1204-1215</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract><![CDATA[The escalating demand for high-resolution sensor interface systems, driven by the proliferation of the Internet of Things (IoT) and wearable smart devices, has led to the widespread use of capacitive sensing transducers. These transducers are valued for their low-noise and low-power characteristics, making them suitable for various applications, including environmental and biomedical sensing. However, designing a high-resolution capacitive sensor interface system while maintaining power efficiency remains challenging. This article proposes a high-resolution energy-efficient highpass (HP) <inline-formula> <tex-math notation="LaTeX">\Delta \Sigma </tex-math></inline-formula> capacitance-to-digital converter (CDC) architecture. The architecture incorporates a 2nd-order HP <inline-formula> <tex-math notation="LaTeX">\Delta \Sigma </tex-math></inline-formula> modulator (<inline-formula> <tex-math notation="LaTeX">\Delta \Sigma \text{M} </tex-math></inline-formula>) and a continuous-time capacitance-to-voltage converter (CT CVC). The proposed CDC achieves an excellent capacitance resolution of 5.85 aFrms, with a power efficiency of 46 fJ/conversion-step and an FoMS of 187.4 dB. The HP <inline-formula> <tex-math notation="LaTeX">\Delta \Sigma \text{M} </tex-math></inline-formula>, designed with superior power efficiency, offers a promising solution for high-resolution capacitive sensor applications. Compared to state-of-the-art, the proposed CDC achieves more than 2<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> FoMS improvement while maintaining competitive FoMW.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2024.3353008</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0002-1540-5102</orcidid><orcidid>https://orcid.org/0000-0003-3589-086X</orcidid><orcidid>https://orcid.org/0000-0003-0461-6729</orcidid><orcidid>https://orcid.org/0000-0003-4580-2771</orcidid></addata></record> |
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| subjects | Capacitance capacitance-to-digital converter (CDC) Capacitive sensors Efficiency Harmonic analysis High resolution highpass (HP) ΔΣ CDC highpass ΔΣM Integrated circuits Internet of Things Internet of Things (IoT) Power harmonic filters Power management sensor interface integrated circuit (IC) Sensors Topology Transducers Voltage converters ΔΣ modulator (ΔΣM) |
| title | A 187-dB FoMS Power-Efficient Second-Order Highpass ΔΣ Capacitance-to-Digital Converter |
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