Cost-Efficient Solution to Overcome Latch-Up Path in 5 V-Tolerant I/O With Low-Voltage Biased NBL Isolation Ring in a 0.18-μm BCD Technology

For IC products, the I/O pins of CMOS integrated circuits (ICs) must be verified by latch-up I-test with the JEDEC JESD78F.01 standard. The high-voltage (HV) circuits and the low-voltage (LV) circuits have been integrated together in a single chip by the Bipolar-CMOS-DMOS (BCD) technology. The LV ci...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	IEEE transactions on electron devices 2024-03, Vol.71 (3), p.2224-2227
Hauptverfasser:	Hsu, Chen-Wei, Ker, Ming-Dou
Format:	Artikel
Sprache:	eng
Schlagworte:	Bipolar-CMOS-DMOS (BCD) technology CMOS Current measurement Electric potential I/O pad Integrated circuits Latch-up Layout n-type buried layer (NBL) isolation ring Schottky barrier diode (SBD) silicon-controlled-rectifier (SCR) Structural rings Substrates Temperature measurement Voltage
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Schreiben Sie den ersten Kommentar!