Theoretical Analysis and Experimental Characterization of 1.2-kV 4H-SiC Planar Split-Gate MOSFET With Source Field Plate
The 1.2-kV-rated 4H-SiC planar split-gate (SG) MOSFET embedding source field plate incorporated between separated gates (termed SFP-SG-MOSFET) is proposed and demonstrated. The utilization of the embedding source field plate in conventional SG-MOSFET (Conv-SG-MOSFETs) serves to alleviate the adverse...
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| Veröffentlicht in: | IEEE transactions on electron devices 2024-03, Vol.71 (3), p.1508-1512 |
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| creator | Yu, Hengyu Wang, Jun Zhang, Jinyi Liang, Shiwei Shen, Z. John |
| description | The 1.2-kV-rated 4H-SiC planar split-gate (SG) MOSFET embedding source field plate incorporated between separated gates (termed SFP-SG-MOSFET) is proposed and demonstrated. The utilization of the embedding source field plate in conventional SG-MOSFET (Conv-SG-MOSFETs) serves to alleviate the adverse effects of electric field crowding. It also maintains the minimum reverse transfer capacitance ( {C}_{\text {rss}}{)} . As a result, the high-frequency figure-of-merit (HF-FOM) and switching efficiency of the proposed SFP-SG MOSFET are improved compared to those of a conventional planar-gate MOSFET (Conv-PG-MOSFET) while maintaining the same blocking voltage rating. The experimental results demonstrate that {C}_{\text {rss}} of the fabricated devices is reduced by 80% and 53% at {V}_{\text {ds}} = 0 V and {V}_{\text {ds}} = 800 V, respectively. Thus, the SFP-SG-MOSFET exhibits HF-FOMs < {R}_{\text {ON}} \times {C}_{\text {rss}}> 4.9 times lower at {V}_{\text {ds}} = 0 V and 2.0 times lower at {V}_{\text {ds}} = 800 V. Furthermore, the switching loss of the SFP-SG-MOSFET is reduced by 25%. This makes it possible for the proposed devices to handle a higher power density. |
| doi_str_mv | 10.1109/TED.2023.3336644 |
| format | Article |
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John</creator><creatorcontrib>Yu, Hengyu ; Wang, Jun ; Zhang, Jinyi ; Liang, Shiwei ; Shen, Z. John</creatorcontrib><description><![CDATA[The 1.2-kV-rated 4H-SiC planar split-gate (SG) MOSFET embedding source field plate incorporated between separated gates (termed SFP-SG-MOSFET) is proposed and demonstrated. The utilization of the embedding source field plate in conventional SG-MOSFET (Conv-SG-MOSFETs) serves to alleviate the adverse effects of electric field crowding. It also maintains the minimum reverse transfer capacitance (<inline-formula> <tex-math notation="LaTeX">{C}_{\text {rss}}{)} </tex-math></inline-formula>. As a result, the high-frequency figure-of-merit (HF-FOM) and switching efficiency of the proposed SFP-SG MOSFET are improved compared to those of a conventional planar-gate MOSFET (Conv-PG-MOSFET) while maintaining the same blocking voltage rating. The experimental results demonstrate that <inline-formula> <tex-math notation="LaTeX">{C}_{\text {rss}} </tex-math></inline-formula> of the fabricated devices is reduced by 80% and 53% at <inline-formula> <tex-math notation="LaTeX">{V}_{\text {ds}} </tex-math></inline-formula> = 0 V and <inline-formula> <tex-math notation="LaTeX">{V}_{\text {ds}} </tex-math></inline-formula> = 800 V, respectively. Thus, the SFP-SG-MOSFET exhibits HF-FOMs <inline-formula> <tex-math notation="LaTeX"> < {R}_{\text {ON}} \times {C}_{\text {rss}}> </tex-math></inline-formula> 4.9 times lower at <inline-formula> <tex-math notation="LaTeX">{V}_{\text {ds}} </tex-math></inline-formula> = 0 V and 2.0 times lower at <inline-formula> <tex-math notation="LaTeX">{V}_{\text {ds}} </tex-math></inline-formula> = 800 V. Furthermore, the switching loss of the SFP-SG-MOSFET is reduced by 25%. This makes it possible for the proposed devices to handle a higher power density.]]></description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2023.3336644</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>4H-SiC MOSFET ; Capacitance ; Electric fields ; Embedding ; Figure of merit ; high-frequency figure-of-merits (HF-FOMs) ; JFETs ; Logic gates ; MOSFET ; MOSFETs ; Silicon carbide ; source field plate ; split gate (SG) ; Switches ; Switching ; switching loss</subject><ispartof>IEEE transactions on electron devices, 2024-03, Vol.71 (3), p.1508-1512</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2024</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c245t-fcc2fb655412623d57ea1836dba090536955f039e82d057aaf4ca2e2f4f155ae3</cites><orcidid>0000-0002-7511-5553 ; 0000-0002-4679-8180 ; 0000-0002-3299-8106 ; 0000-0002-5470-5984</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10335634$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,781,785,797,27929,27930,54763</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10335634$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yu, Hengyu</creatorcontrib><creatorcontrib>Wang, Jun</creatorcontrib><creatorcontrib>Zhang, Jinyi</creatorcontrib><creatorcontrib>Liang, Shiwei</creatorcontrib><creatorcontrib>Shen, Z. John</creatorcontrib><title>Theoretical Analysis and Experimental Characterization of 1.2-kV 4H-SiC Planar Split-Gate MOSFET With Source Field Plate</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description><![CDATA[The 1.2-kV-rated 4H-SiC planar split-gate (SG) MOSFET embedding source field plate incorporated between separated gates (termed SFP-SG-MOSFET) is proposed and demonstrated. The utilization of the embedding source field plate in conventional SG-MOSFET (Conv-SG-MOSFETs) serves to alleviate the adverse effects of electric field crowding. It also maintains the minimum reverse transfer capacitance (<inline-formula> <tex-math notation="LaTeX">{C}_{\text {rss}}{)} </tex-math></inline-formula>. As a result, the high-frequency figure-of-merit (HF-FOM) and switching efficiency of the proposed SFP-SG MOSFET are improved compared to those of a conventional planar-gate MOSFET (Conv-PG-MOSFET) while maintaining the same blocking voltage rating. The experimental results demonstrate that <inline-formula> <tex-math notation="LaTeX">{C}_{\text {rss}} </tex-math></inline-formula> of the fabricated devices is reduced by 80% and 53% at <inline-formula> <tex-math notation="LaTeX">{V}_{\text {ds}} </tex-math></inline-formula> = 0 V and <inline-formula> <tex-math notation="LaTeX">{V}_{\text {ds}} </tex-math></inline-formula> = 800 V, respectively. Thus, the SFP-SG-MOSFET exhibits HF-FOMs <inline-formula> <tex-math notation="LaTeX"> < {R}_{\text {ON}} \times {C}_{\text {rss}}> </tex-math></inline-formula> 4.9 times lower at <inline-formula> <tex-math notation="LaTeX">{V}_{\text {ds}} </tex-math></inline-formula> = 0 V and 2.0 times lower at <inline-formula> <tex-math notation="LaTeX">{V}_{\text {ds}} </tex-math></inline-formula> = 800 V. Furthermore, the switching loss of the SFP-SG-MOSFET is reduced by 25%. This makes it possible for the proposed devices to handle a higher power density.]]></description><subject>4H-SiC MOSFET</subject><subject>Capacitance</subject><subject>Electric fields</subject><subject>Embedding</subject><subject>Figure of merit</subject><subject>high-frequency figure-of-merits (HF-FOMs)</subject><subject>JFETs</subject><subject>Logic gates</subject><subject>MOSFET</subject><subject>MOSFETs</subject><subject>Silicon carbide</subject><subject>source field plate</subject><subject>split gate (SG)</subject><subject>Switches</subject><subject>Switching</subject><subject>switching loss</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkE1LAzEQhoMoWKt3Dx4Cnrfmu7tHqa0VKhW26nEZdyc0uu7WJIXqrzelHjwNM3lmyPsQcsnZiHNW3KymdyPBhBxJKY1R6ogMuNbjrDDKHJMBYzzPCpnLU3IWwntqEyMGZLdaY-8xuhpaettB-x1coNA1dLrboHef2MX0MlmDhzqmwQ9E13e0t5SPRPbxQtU8K92EPrXQgaflpnUxu4eI9HFZzqYr-urimpb91tdIZw7bZo9GPCcnFtqAF391SJ4TPZlni-X9w-R2kdVC6ZjZuhb2zWituDBCNnqMwHNpmjdgBdPSFFpbJgvMRcP0GMCqGgQKq2yKDyiH5Ppwd-P7ry2GWL2nv6SgoRJFUsWSIJ4odqBq34fg0VablB38d8VZtfdbJb_V3m_15zetXB1WHCL-w6XURir5C7o_dSA</recordid><startdate>20240301</startdate><enddate>20240301</enddate><creator>Yu, Hengyu</creator><creator>Wang, Jun</creator><creator>Zhang, Jinyi</creator><creator>Liang, Shiwei</creator><creator>Shen, Z. John</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-7511-5553</orcidid><orcidid>https://orcid.org/0000-0002-4679-8180</orcidid><orcidid>https://orcid.org/0000-0002-3299-8106</orcidid><orcidid>https://orcid.org/0000-0002-5470-5984</orcidid></search><sort><creationdate>20240301</creationdate><title>Theoretical Analysis and Experimental Characterization of 1.2-kV 4H-SiC Planar Split-Gate MOSFET With Source Field Plate</title><author>Yu, Hengyu ; Wang, Jun ; Zhang, Jinyi ; Liang, Shiwei ; Shen, Z. John</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c245t-fcc2fb655412623d57ea1836dba090536955f039e82d057aaf4ca2e2f4f155ae3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>4H-SiC MOSFET</topic><topic>Capacitance</topic><topic>Electric fields</topic><topic>Embedding</topic><topic>Figure of merit</topic><topic>high-frequency figure-of-merits (HF-FOMs)</topic><topic>JFETs</topic><topic>Logic gates</topic><topic>MOSFET</topic><topic>MOSFETs</topic><topic>Silicon carbide</topic><topic>source field plate</topic><topic>split gate (SG)</topic><topic>Switches</topic><topic>Switching</topic><topic>switching loss</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Yu, Hengyu</creatorcontrib><creatorcontrib>Wang, Jun</creatorcontrib><creatorcontrib>Zhang, Jinyi</creatorcontrib><creatorcontrib>Liang, Shiwei</creatorcontrib><creatorcontrib>Shen, Z. John</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005–Present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yu, Hengyu</au><au>Wang, Jun</au><au>Zhang, Jinyi</au><au>Liang, Shiwei</au><au>Shen, Z. John</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Theoretical Analysis and Experimental Characterization of 1.2-kV 4H-SiC Planar Split-Gate MOSFET With Source Field Plate</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2024-03-01</date><risdate>2024</risdate><volume>71</volume><issue>3</issue><spage>1508</spage><epage>1512</epage><pages>1508-1512</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract><![CDATA[The 1.2-kV-rated 4H-SiC planar split-gate (SG) MOSFET embedding source field plate incorporated between separated gates (termed SFP-SG-MOSFET) is proposed and demonstrated. The utilization of the embedding source field plate in conventional SG-MOSFET (Conv-SG-MOSFETs) serves to alleviate the adverse effects of electric field crowding. It also maintains the minimum reverse transfer capacitance (<inline-formula> <tex-math notation="LaTeX">{C}_{\text {rss}}{)} </tex-math></inline-formula>. As a result, the high-frequency figure-of-merit (HF-FOM) and switching efficiency of the proposed SFP-SG MOSFET are improved compared to those of a conventional planar-gate MOSFET (Conv-PG-MOSFET) while maintaining the same blocking voltage rating. The experimental results demonstrate that <inline-formula> <tex-math notation="LaTeX">{C}_{\text {rss}} </tex-math></inline-formula> of the fabricated devices is reduced by 80% and 53% at <inline-formula> <tex-math notation="LaTeX">{V}_{\text {ds}} </tex-math></inline-formula> = 0 V and <inline-formula> <tex-math notation="LaTeX">{V}_{\text {ds}} </tex-math></inline-formula> = 800 V, respectively. Thus, the SFP-SG-MOSFET exhibits HF-FOMs <inline-formula> <tex-math notation="LaTeX"> < {R}_{\text {ON}} \times {C}_{\text {rss}}> </tex-math></inline-formula> 4.9 times lower at <inline-formula> <tex-math notation="LaTeX">{V}_{\text {ds}} </tex-math></inline-formula> = 0 V and 2.0 times lower at <inline-formula> <tex-math notation="LaTeX">{V}_{\text {ds}} </tex-math></inline-formula> = 800 V. Furthermore, the switching loss of the SFP-SG-MOSFET is reduced by 25%. This makes it possible for the proposed devices to handle a higher power density.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2023.3336644</doi><tpages>5</tpages><orcidid>https://orcid.org/0000-0002-7511-5553</orcidid><orcidid>https://orcid.org/0000-0002-4679-8180</orcidid><orcidid>https://orcid.org/0000-0002-3299-8106</orcidid><orcidid>https://orcid.org/0000-0002-5470-5984</orcidid></addata></record> |
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| subjects | 4H-SiC MOSFET Capacitance Electric fields Embedding Figure of merit high-frequency figure-of-merits (HF-FOMs) JFETs Logic gates MOSFET MOSFETs Silicon carbide source field plate split gate (SG) Switches Switching switching loss |
| title | Theoretical Analysis and Experimental Characterization of 1.2-kV 4H-SiC Planar Split-Gate MOSFET With Source Field Plate |
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