Power efficient MPEG-4 decoder architecture featuring low-complexity error resilience
A media processor supporting MPEG-4 SP@LI and H.263 baseline has been developed. This processor includes a RISC core, dedicated video decoding hardware, audio/voice decoder, post processor, and some peripherals. In order to increase flexibility and reduce power dissipation, separated bus architectur...
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| creator | Byun, H.I. Jeon, M.Y. Seo, J.Y. Lee, K.W. Lee, S.H. Kang, B.H. |
| description | A media processor supporting MPEG-4 SP@LI and H.263 baseline has been developed. This processor includes a RISC core, dedicated video decoding hardware, audio/voice decoder, post processor, and some peripherals. In order to increase flexibility and reduce power dissipation, separated bus architecture, which may minimize the bus transaction, is adopted. An enhanced error resiliency is also equipped for error-prone environment, and additional innovative low-power design techniques are applied for portable applications. This processor was integrated in a 0.25/spl mu/m CMOS PLM process and contains 900K gates on 45mm/sup 2/ die with 50mW power dissipation at 27MHz. |
| doi_str_mv | 10.1109/APASIC.2002.1031573 |
| format | Conference Proceeding |
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| language | eng |
| recordid | cdi_ieee_primary_1031573 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks Codecs Coprocessors Decoding Energy consumption MPEG 4 Standard Process control Reduced instruction set computing Resilience SDRAM |
| title | Power efficient MPEG-4 decoder architecture featuring low-complexity error resilience |
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