Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks
Binary neural networks (BNNs) largely reduce the memory footprint and computational complexity, so they are gaining interests on various mobile applications. In the BNNs, the first layer often accounts for the largest part of the entire computing time because the layer usually uses multi-bit multipl...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2023-12, Vol.31 (12), p.2137-2141 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Ryu, Sungju Oh, Youngtaek Kim, Jae-Joon |
| description | Binary neural networks (BNNs) largely reduce the memory footprint and computational complexity, so they are gaining interests on various mobile applications. In the BNNs, the first layer often accounts for the largest part of the entire computing time because the layer usually uses multi-bit multiplications. However, traditional hardware designed for BNN computing focuses primarily on the rest layers, resulting in significant performance degradation. In this brief, we introduce Binaryware architecture which achieves the high-performance computation on both the first and rest layers. Experimental results show that our Binaryware improves the throughput per compute area by 1.5- 13.3\times on various BNN workloads. |
| doi_str_mv | 10.1109/TVLSI.2023.3324834 |
| format | Article |
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| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2023-12, Vol.31 (12), p.2137-2141 |
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| source | IEEE Electronic Library (IEL) |
| subjects | Adders Applications programs Artificial intelligence binary neural networks (BNNs) Computer architecture Computing time Energy efficiency Hardware Hardware acceleration hardware accelerator Logic gates Mobile computing Neural networks Performance degradation quantization Random access memory |
| title | Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks |
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