Power analysis techniques for SoC with improved wiring models

This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets; and (2) the use of layout information (actual net capacitance and input signal transition time). The analysis time is red...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Sakamoto, T., Yamada, T., Mukuno, M., Matsushita, Y., Harada, Y., Yasuura, H.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Capacitance Clocks Error analysis Information analysis Load modeling Power system modeling Signal analysis System-on-a-chip Wire Wiring
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