Power analysis techniques for SoC with improved wiring models
This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets; and (2) the use of layout information (actual net capacitance and input signal transition time). The analysis time is red...
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| creator | Sakamoto, T. Yamada, T. Mukuno, M. Matsushita, Y. Harada, Y. Yasuura, H. |
| description | This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets; and (2) the use of layout information (actual net capacitance and input signal transition time). The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. The error is within 5% of that of a real chip, (the same level in transistor-level power analysis) if technique (2) is used. The analytical error between technique (1) and (2) is within 1%. |
| doi_str_mv | 10.1109/LPE.2002.146750 |
| format | Conference Proceeding |
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(1) The creation of custom wire load models for clock nets; and (2) the use of layout information (actual net capacitance and input signal transition time). The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. The error is within 5% of that of a real chip, (the same level in transistor-level power analysis) if technique (2) is used. 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The analytical error between technique (1) and (2) is within 1%.</description><subject>Capacitance</subject><subject>Clocks</subject><subject>Error analysis</subject><subject>Information analysis</subject><subject>Load modeling</subject><subject>Power system modeling</subject><subject>Signal analysis</subject><subject>System-on-a-chip</subject><subject>Wire</subject><subject>Wiring</subject><isbn>1581134754</isbn><isbn>9781581134759</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2002</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjstKw0AUQAdEUGvXLtzMDyTeO69kFi4kVCsELKjrMsnc2JE86ky19O8N6OpwNofD2A1Cjgj2rt6scgEgclSm0HDGrlCXiFIVWl2wZUqfADB7URZ4ye4305Eid6PrTykkfqB2N4avb0q8myJ_nSp-DIcdD8M-Tj_kZ4th_ODD5KlP1-y8c32i5T8X7P1x9Vats_rl6bl6qLOAwkJGopGNa0yHxsL80TbOGdsKpwxY70vfqcJYr8nIFhtVgm81kS6kws550HLBbv-6gYi2-xgGF09bBGENGvkLlXNGcw</recordid><startdate>2002</startdate><enddate>2002</enddate><creator>Sakamoto, T.</creator><creator>Yamada, T.</creator><creator>Mukuno, M.</creator><creator>Matsushita, Y.</creator><creator>Harada, Y.</creator><creator>Yasuura, H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2002</creationdate><title>Power analysis techniques for SoC with improved wiring models</title><author>Sakamoto, T. ; Yamada, T. ; Mukuno, M. ; Matsushita, Y. ; Harada, Y. ; Yasuura, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i1290-e2b3bab6f1690475cbaa69c2a4609dd8df4769d5e63c1b480dc5ee57341fad053</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Capacitance</topic><topic>Clocks</topic><topic>Error analysis</topic><topic>Information analysis</topic><topic>Load modeling</topic><topic>Power system modeling</topic><topic>Signal analysis</topic><topic>System-on-a-chip</topic><topic>Wire</topic><topic>Wiring</topic><toplevel>online_resources</toplevel><creatorcontrib>Sakamoto, T.</creatorcontrib><creatorcontrib>Yamada, T.</creatorcontrib><creatorcontrib>Mukuno, M.</creatorcontrib><creatorcontrib>Matsushita, Y.</creatorcontrib><creatorcontrib>Harada, Y.</creatorcontrib><creatorcontrib>Yasuura, H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sakamoto, T.</au><au>Yamada, T.</au><au>Mukuno, M.</au><au>Matsushita, Y.</au><au>Harada, Y.</au><au>Yasuura, H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Power analysis techniques for SoC with improved wiring models</atitle><btitle>Proceedings of the International Symposium on Low Power Electronics and Design</btitle><stitle>LPE</stitle><date>2002</date><risdate>2002</risdate><spage>259</spage><epage>262</epage><pages>259-262</pages><isbn>1581134754</isbn><isbn>9781581134759</isbn><abstract>This paper proposes two techniques for improving the accuracy of gate-level power analysis for system-on-a-chip (SoC). (1) The creation of custom wire load models for clock nets; and (2) the use of layout information (actual net capacitance and input signal transition time). The analysis time is reduced to less than one three-hundredth of the transistor-level power analysis time. The error is within 5% of that of a real chip, (the same level in transistor-level power analysis) if technique (2) is used. The analytical error between technique (1) and (2) is within 1%.</abstract><pub>IEEE</pub><doi>10.1109/LPE.2002.146750</doi><tpages>4</tpages><oa>free_for_read</oa></addata></record> |
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| subjects | Capacitance Clocks Error analysis Information analysis Load modeling Power system modeling Signal analysis System-on-a-chip Wire Wiring |
| title | Power analysis techniques for SoC with improved wiring models |
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