FSPDA: A Full Sequence Program Data Allocation Scheme for boosting 3D NAND Flash Read Performance

Multi-bit 3D NAND flash-based SSDs, offering high storage density, contain multiple types of pages to accommodate multiple bits per physical cell. Full sequence program or FSP can program multiple pages in a word line at a time, thereby improving write throughput. Unfortunately, large-grained FSP operations coarsely aggregate consecutive logical pages on the same word line, which adversely affects the parallelism and latency of read requests. Moreover, FSP smooths the program latencies for different types of pages, whereas the pages still exhibit various read latencies. Multiple read latencies and lower read parallelism noticeably deteriorate the completion efficiency of read requests: SSD performance is degraded. To address this issue, we propose a full sequence program data allocation scheme called FSPDA that incorporates the physical structure characteristics of multi-bit 3D NAND, aiming to bolster the read performance of 3D NAND Flash-based SSDs. FSPDA embraces two distinctive and vital features. First, according to the distance between logical pages, FSPDA allocates logical pages to specified parallel units and stipulates that consecutive logical pages must be assigned to different planes, thus improving read parallelism and data locality. Second, to further reduce read latency, FSPDA employs cache hits to determine hot and cold data to be placed to low-latency and high-latency pages, respectively. We compare FSPDA with two state-of-art schemes - OSPADA and SOML - in terms of multi-plane read counts, read response time, and GC counts under eight real-world workloads. The experimental results show that compared with the existing schemes, FSPDA slashes the number of multi-plane read counts, read response time, and the number of GC counts by an average of 34.4%, 28.5%, and 13.6%, respectively.