Influence of Free Layer Surface Roughness on Magnetic and Electrical Properties of 300 mm CMOS-compatible MTJ Stacks
The magnetic tunnel junction (MTJ) is a highly versatile device widely used in today's spintronic applications such as magnetoresistive random-access memory (MRAM), magnetic sensors and prospectively as a read device in racetrack memory. Tuning the perpendicular (p-)MTJ stack to match the desir...
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Veröffentlicht in: | IEEE transactions on magnetics 2023-11, Vol.59 (11), p.1-1 |
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creator | Durner, Christoph Lederer, Maximilian Gurieva, Tatiana Hertel, Johannes Hindenberg, Meike Gerlich, Lukas Wagner-Reetz, Maik Parkin, Stuart |
description | The magnetic tunnel junction (MTJ) is a highly versatile device widely used in today's spintronic applications such as magnetoresistive random-access memory (MRAM), magnetic sensors and prospectively as a read device in racetrack memory. Tuning the perpendicular (p-)MTJ stack to match the desired properties, such as tunnel magnetoresistance (TMR), magnetic anisotropies or coercive field of the free layer, requires careful optimization of the deposition parameters as well as precise layer thickness control. Here, the deposition of individual layers in a wedged manner across 300 mm wafers is proposed to engineer the thicknesses within the stack more efficiently. Furthermore, this technique provides detailed insights into effects related to surface roughness, magnetic anisotropy and TMR. |
doi_str_mv | 10.1109/TMAG.2023.3287134 |
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fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_10154176</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>10154176</ieee_id><sourcerecordid>2881502533</sourcerecordid><originalsourceid>FETCH-LOGICAL-c342t-b666f97fcb6535953c959b08dd043ee52cddb92d20da8110c1caea870cf3cf4e3</originalsourceid><addsrcrecordid>eNpNkE1Lw0AQhhdRsFZ_gOBhwXPqfibZYym1Vhoqtp7DZjNbU_PlbnLovzehPXgaZnjed-BB6JGSGaVEveyT-WrGCOMzzuKIcnGFJlQJGhASqms0IYTGgRKhuEV33h-HVUhKJqhb17bsoTaAG4tfHQDe6BM4vOud1cP1s-kP3zV4j5saJ_pQQ1cYrOscL0swnSuMLvGHa1pwXQF-bOGE4KrCi2S7C0xTtborshJwsn_Hu06bH3-PbqwuPTxc5hR9vS73i7dgs12tF_NNYLhgXZCFYWhVZE0WSi6V5EZJlZE4z4ngAJKZPM8UyxnJdTxYMNRo0HFEjOXGCuBT9HzubV3z24Pv0mPTu3p4mbI4ppIwyflA0TNlXOO9A5u2rqi0O6WUpKPcdJSbjnLTi9wh83TOFADwj6dS0CjkfypcdVs</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2881502533</pqid></control><display><type>article</type><title>Influence of Free Layer Surface Roughness on Magnetic and Electrical Properties of 300 mm CMOS-compatible MTJ Stacks</title><source>IEEE Electronic Library (IEL)</source><creator>Durner, Christoph ; Lederer, Maximilian ; Gurieva, Tatiana ; Hertel, Johannes ; Hindenberg, Meike ; Gerlich, Lukas ; Wagner-Reetz, Maik ; Parkin, Stuart</creator><creatorcontrib>Durner, Christoph ; Lederer, Maximilian ; Gurieva, Tatiana ; Hertel, Johannes ; Hindenberg, Meike ; Gerlich, Lukas ; Wagner-Reetz, Maik ; Parkin, Stuart</creatorcontrib><description>The magnetic tunnel junction (MTJ) is a highly versatile device widely used in today's spintronic applications such as magnetoresistive random-access memory (MRAM), magnetic sensors and prospectively as a read device in racetrack memory. Tuning the perpendicular (p-)MTJ stack to match the desired properties, such as tunnel magnetoresistance (TMR), magnetic anisotropies or coercive field of the free layer, requires careful optimization of the deposition parameters as well as precise layer thickness control. Here, the deposition of individual layers in a wedged manner across 300 mm wafers is proposed to engineer the thicknesses within the stack more efficiently. Furthermore, this technique provides detailed insights into effects related to surface roughness, magnetic anisotropy and TMR.</description><identifier>ISSN: 0018-9464</identifier><identifier>EISSN: 1941-0069</identifier><identifier>DOI: 10.1109/TMAG.2023.3287134</identifier><identifier>CODEN: IEMGAQ</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>CMOS technology ; Coercivity ; Deposition ; Electrical properties ; Electrical resistance measurement ; Extraterrestrial measurements ; Magnetic anisotropy ; Magnetic field measurement ; Magnetic properties ; magnetic tunnel junctions (MTJs) ; Magnetic tunneling ; Magnetism ; Magnetization ; Magnetoresistivity ; Optimization ; perpendicular magnetic anisotropy ; Random access memory ; Resistance ; Surface roughness ; Thickness ; Thickness measurement ; Tunnel junctions ; Tunnel magnetoresistance</subject><ispartof>IEEE transactions on magnetics, 2023-11, Vol.59 (11), p.1-1</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2023</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c342t-b666f97fcb6535953c959b08dd043ee52cddb92d20da8110c1caea870cf3cf4e3</citedby><cites>FETCH-LOGICAL-c342t-b666f97fcb6535953c959b08dd043ee52cddb92d20da8110c1caea870cf3cf4e3</cites><orcidid>0000-0003-4702-6139 ; 0009-0006-7863-6043 ; 0000-0002-7002-3967 ; 0000-0002-1739-2747 ; 0000-0001-9750-1861</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10154176$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10154176$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Durner, Christoph</creatorcontrib><creatorcontrib>Lederer, Maximilian</creatorcontrib><creatorcontrib>Gurieva, Tatiana</creatorcontrib><creatorcontrib>Hertel, Johannes</creatorcontrib><creatorcontrib>Hindenberg, Meike</creatorcontrib><creatorcontrib>Gerlich, Lukas</creatorcontrib><creatorcontrib>Wagner-Reetz, Maik</creatorcontrib><creatorcontrib>Parkin, Stuart</creatorcontrib><title>Influence of Free Layer Surface Roughness on Magnetic and Electrical Properties of 300 mm CMOS-compatible MTJ Stacks</title><title>IEEE transactions on magnetics</title><addtitle>TMAG</addtitle><description>The magnetic tunnel junction (MTJ) is a highly versatile device widely used in today's spintronic applications such as magnetoresistive random-access memory (MRAM), magnetic sensors and prospectively as a read device in racetrack memory. Tuning the perpendicular (p-)MTJ stack to match the desired properties, such as tunnel magnetoresistance (TMR), magnetic anisotropies or coercive field of the free layer, requires careful optimization of the deposition parameters as well as precise layer thickness control. Here, the deposition of individual layers in a wedged manner across 300 mm wafers is proposed to engineer the thicknesses within the stack more efficiently. Furthermore, this technique provides detailed insights into effects related to surface roughness, magnetic anisotropy and TMR.</description><subject>CMOS technology</subject><subject>Coercivity</subject><subject>Deposition</subject><subject>Electrical properties</subject><subject>Electrical resistance measurement</subject><subject>Extraterrestrial measurements</subject><subject>Magnetic anisotropy</subject><subject>Magnetic field measurement</subject><subject>Magnetic properties</subject><subject>magnetic tunnel junctions (MTJs)</subject><subject>Magnetic tunneling</subject><subject>Magnetism</subject><subject>Magnetization</subject><subject>Magnetoresistivity</subject><subject>Optimization</subject><subject>perpendicular magnetic anisotropy</subject><subject>Random access memory</subject><subject>Resistance</subject><subject>Surface roughness</subject><subject>Thickness</subject><subject>Thickness measurement</subject><subject>Tunnel junctions</subject><subject>Tunnel magnetoresistance</subject><issn>0018-9464</issn><issn>1941-0069</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkE1Lw0AQhhdRsFZ_gOBhwXPqfibZYym1Vhoqtp7DZjNbU_PlbnLovzehPXgaZnjed-BB6JGSGaVEveyT-WrGCOMzzuKIcnGFJlQJGhASqms0IYTGgRKhuEV33h-HVUhKJqhb17bsoTaAG4tfHQDe6BM4vOud1cP1s-kP3zV4j5saJ_pQQ1cYrOscL0swnSuMLvGHa1pwXQF-bOGE4KrCi2S7C0xTtborshJwsn_Hu06bH3-PbqwuPTxc5hR9vS73i7dgs12tF_NNYLhgXZCFYWhVZE0WSi6V5EZJlZE4z4ngAJKZPM8UyxnJdTxYMNRo0HFEjOXGCuBT9HzubV3z24Pv0mPTu3p4mbI4ppIwyflA0TNlXOO9A5u2rqi0O6WUpKPcdJSbjnLTi9wh83TOFADwj6dS0CjkfypcdVs</recordid><startdate>20231101</startdate><enddate>20231101</enddate><creator>Durner, Christoph</creator><creator>Lederer, Maximilian</creator><creator>Gurieva, Tatiana</creator><creator>Hertel, Johannes</creator><creator>Hindenberg, Meike</creator><creator>Gerlich, Lukas</creator><creator>Wagner-Reetz, Maik</creator><creator>Parkin, Stuart</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7U5</scope><scope>8BQ</scope><scope>8FD</scope><scope>JG9</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-4702-6139</orcidid><orcidid>https://orcid.org/0009-0006-7863-6043</orcidid><orcidid>https://orcid.org/0000-0002-7002-3967</orcidid><orcidid>https://orcid.org/0000-0002-1739-2747</orcidid><orcidid>https://orcid.org/0000-0001-9750-1861</orcidid></search><sort><creationdate>20231101</creationdate><title>Influence of Free Layer Surface Roughness on Magnetic and Electrical Properties of 300 mm CMOS-compatible MTJ Stacks</title><author>Durner, Christoph ; Lederer, Maximilian ; Gurieva, Tatiana ; Hertel, Johannes ; Hindenberg, Meike ; Gerlich, Lukas ; Wagner-Reetz, Maik ; Parkin, Stuart</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c342t-b666f97fcb6535953c959b08dd043ee52cddb92d20da8110c1caea870cf3cf4e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2023</creationdate><topic>CMOS technology</topic><topic>Coercivity</topic><topic>Deposition</topic><topic>Electrical properties</topic><topic>Electrical resistance measurement</topic><topic>Extraterrestrial measurements</topic><topic>Magnetic anisotropy</topic><topic>Magnetic field measurement</topic><topic>Magnetic properties</topic><topic>magnetic tunnel junctions (MTJs)</topic><topic>Magnetic tunneling</topic><topic>Magnetism</topic><topic>Magnetization</topic><topic>Magnetoresistivity</topic><topic>Optimization</topic><topic>perpendicular magnetic anisotropy</topic><topic>Random access memory</topic><topic>Resistance</topic><topic>Surface roughness</topic><topic>Thickness</topic><topic>Thickness measurement</topic><topic>Tunnel junctions</topic><topic>Tunnel magnetoresistance</topic><toplevel>online_resources</toplevel><creatorcontrib>Durner, Christoph</creatorcontrib><creatorcontrib>Lederer, Maximilian</creatorcontrib><creatorcontrib>Gurieva, Tatiana</creatorcontrib><creatorcontrib>Hertel, Johannes</creatorcontrib><creatorcontrib>Hindenberg, Meike</creatorcontrib><creatorcontrib>Gerlich, Lukas</creatorcontrib><creatorcontrib>Wagner-Reetz, Maik</creatorcontrib><creatorcontrib>Parkin, Stuart</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>Materials Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on magnetics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Durner, Christoph</au><au>Lederer, Maximilian</au><au>Gurieva, Tatiana</au><au>Hertel, Johannes</au><au>Hindenberg, Meike</au><au>Gerlich, Lukas</au><au>Wagner-Reetz, Maik</au><au>Parkin, Stuart</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Influence of Free Layer Surface Roughness on Magnetic and Electrical Properties of 300 mm CMOS-compatible MTJ Stacks</atitle><jtitle>IEEE transactions on magnetics</jtitle><stitle>TMAG</stitle><date>2023-11-01</date><risdate>2023</risdate><volume>59</volume><issue>11</issue><spage>1</spage><epage>1</epage><pages>1-1</pages><issn>0018-9464</issn><eissn>1941-0069</eissn><coden>IEMGAQ</coden><abstract>The magnetic tunnel junction (MTJ) is a highly versatile device widely used in today's spintronic applications such as magnetoresistive random-access memory (MRAM), magnetic sensors and prospectively as a read device in racetrack memory. Tuning the perpendicular (p-)MTJ stack to match the desired properties, such as tunnel magnetoresistance (TMR), magnetic anisotropies or coercive field of the free layer, requires careful optimization of the deposition parameters as well as precise layer thickness control. Here, the deposition of individual layers in a wedged manner across 300 mm wafers is proposed to engineer the thicknesses within the stack more efficiently. Furthermore, this technique provides detailed insights into effects related to surface roughness, magnetic anisotropy and TMR.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TMAG.2023.3287134</doi><tpages>1</tpages><orcidid>https://orcid.org/0000-0003-4702-6139</orcidid><orcidid>https://orcid.org/0009-0006-7863-6043</orcidid><orcidid>https://orcid.org/0000-0002-7002-3967</orcidid><orcidid>https://orcid.org/0000-0002-1739-2747</orcidid><orcidid>https://orcid.org/0000-0001-9750-1861</orcidid></addata></record> |
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subjects | CMOS technology Coercivity Deposition Electrical properties Electrical resistance measurement Extraterrestrial measurements Magnetic anisotropy Magnetic field measurement Magnetic properties magnetic tunnel junctions (MTJs) Magnetic tunneling Magnetism Magnetization Magnetoresistivity Optimization perpendicular magnetic anisotropy Random access memory Resistance Surface roughness Thickness Thickness measurement Tunnel junctions Tunnel magnetoresistance |
title | Influence of Free Layer Surface Roughness on Magnetic and Electrical Properties of 300 mm CMOS-compatible MTJ Stacks |
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