A non-linearity self-calibration technique for delay-locked loop delay-lines

An on-chip non-linearity self-calibration of a CMOS all-digital shunt capacitor delay-line is achieved by first measuring the non-linearity of each delay-cell by means of a statistical test and then correcting the individual cell delay mismatch according to the test results. An iterative calibration...

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Bibliographische Detailangaben

Hauptverfasser:	Baronti, F., Fanucci, L., Lunardini, D., Roncella, R., Saletti, R.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Algorithm design and analysis Automatic testing Calibration Capacitors Circuit testing Delay Digital circuits Digital control Iterative algorithms Silicon
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