Improving the Heat Dissipation and Current Rating of Ga O Schottky Diodes by Substrate Thinning and Junction-Side Cooling
Gallium oxide (Ga _{2} O_{3}) is attractive as a material for power electronics but its low thermal conductivity has risen concerns about thermal management problems. This paper provides a direct evaluation of different assembly strategies for Ga _{2} O_{3} Schottky diodes. 600Mm thick (current stan...
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Veröffentlicht in: | IEEE transactions on power electronics 2023-06, Vol.38 (6), p.1-11 |
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creator | Wilhelmi, Florian Komatsu, Yuji Yamaguchi, Shinya Uchida, Yuki Kase, Tadashi Kunori, Shinji Lindemann, Andreas |
description | Gallium oxide (Ga _{2} O_{3}) is attractive as a material for power electronics but its low thermal conductivity has risen concerns about thermal management problems. This paper provides a direct evaluation of different assembly strategies for Ga _{2} O_{3} Schottky diodes. 600Mm thick (current standard) and novel 200 Mm thin large-area diodes are assembled on ceramic substrates in cathode-side cooling (CSC) and junction-side cooling (JSC) configuration, and compared to a commercial SiC reference diode of similar size that was assembled in the same way, which enables a fair comparison. Thermal imaging and measurements of the thermal structure functions reveal the different contributions of die and package to the total thermal resistance. The lowest junction temperature, close to that of the SiC counterpart, is achieved with junction-side cooling. By combining the measurements with thermal simulations, it is shown that an optimization of the die attach thickness or the use of underfill materials in JSC configuration could further lower the average junction temperature and decrease local temperature peaks significantly. The influence of the assembly method, substrate thickness and on-resistance on the power and current rating of the Ga _{2} O_{3} diodes is discussed for applications where conduction losses dominate. |
doi_str_mv | 10.1109/TPEL.2023.3250026 |
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This paper provides a direct evaluation of different assembly strategies for Ga <inline-formula><tex-math notation="LaTeX">_{2}</tex-math></inline-formula> O<inline-formula><tex-math notation="LaTeX">_{3}</tex-math></inline-formula> Schottky diodes. 600Mm thick (current standard) and novel 200 Mm thin large-area diodes are assembled on ceramic substrates in cathode-side cooling (CSC) and junction-side cooling (JSC) configuration, and compared to a commercial SiC reference diode of similar size that was assembled in the same way, which enables a fair comparison. Thermal imaging and measurements of the thermal structure functions reveal the different contributions of die and package to the total thermal resistance. The lowest junction temperature, close to that of the SiC counterpart, is achieved with junction-side cooling. By combining the measurements with thermal simulations, it is shown that an optimization of the die attach thickness or the use of underfill materials in JSC configuration could further lower the average junction temperature and decrease local temperature peaks significantly. The influence of the assembly method, substrate thickness and on-resistance on the power and current rating of the Ga <inline-formula><tex-math notation="LaTeX">_{2}</tex-math></inline-formula> O<inline-formula><tex-math notation="LaTeX">_{3}</tex-math></inline-formula> diodes is discussed for applications where conduction losses dominate.]]></description><identifier>ISSN: 0885-8993</identifier><identifier>EISSN: 1941-0107</identifier><identifier>DOI: 10.1109/TPEL.2023.3250026</identifier><identifier>CODEN: ITPEE8</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Anodes ; Assembly ; Conduction losses ; Configurations ; Electronic packaging thermal management ; gallium oxide ; Gallium oxides ; Heat transfer ; Optimization ; packaging ; Schottky diodes ; Side cooling ; Silicon carbide ; Substrates ; Thermal conductivity ; Thermal imaging ; Thermal management ; Thermal resistance ; Thermal simulation ; Thickness</subject><ispartof>IEEE transactions on power electronics, 2023-06, Vol.38 (6), p.1-11</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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This paper provides a direct evaluation of different assembly strategies for Ga <inline-formula><tex-math notation="LaTeX">_{2}</tex-math></inline-formula> O<inline-formula><tex-math notation="LaTeX">_{3}</tex-math></inline-formula> Schottky diodes. 600Mm thick (current standard) and novel 200 Mm thin large-area diodes are assembled on ceramic substrates in cathode-side cooling (CSC) and junction-side cooling (JSC) configuration, and compared to a commercial SiC reference diode of similar size that was assembled in the same way, which enables a fair comparison. Thermal imaging and measurements of the thermal structure functions reveal the different contributions of die and package to the total thermal resistance. The lowest junction temperature, close to that of the SiC counterpart, is achieved with junction-side cooling. By combining the measurements with thermal simulations, it is shown that an optimization of the die attach thickness or the use of underfill materials in JSC configuration could further lower the average junction temperature and decrease local temperature peaks significantly. The influence of the assembly method, substrate thickness and on-resistance on the power and current rating of the Ga <inline-formula><tex-math notation="LaTeX">_{2}</tex-math></inline-formula> O<inline-formula><tex-math notation="LaTeX">_{3}</tex-math></inline-formula> diodes is discussed for applications where conduction losses dominate.]]></description><subject>Anodes</subject><subject>Assembly</subject><subject>Conduction losses</subject><subject>Configurations</subject><subject>Electronic packaging thermal management</subject><subject>gallium oxide</subject><subject>Gallium oxides</subject><subject>Heat transfer</subject><subject>Optimization</subject><subject>packaging</subject><subject>Schottky diodes</subject><subject>Side cooling</subject><subject>Silicon carbide</subject><subject>Substrates</subject><subject>Thermal conductivity</subject><subject>Thermal imaging</subject><subject>Thermal management</subject><subject>Thermal resistance</subject><subject>Thermal simulation</subject><subject>Thickness</subject><issn>0885-8993</issn><issn>1941-0107</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkF9PwjAUxRujiYh-ABMfmvg8vP3H1keDCBgSjODz0m2dDKHFtjPZt7cLPPh0k3t_59ycg9A9gREhIJ8279PliAJlI0YFAB1foAGRnCRAIL1EA8gykWRSsmt04_0OgHABZIC6xeHo7G9jvnDYajzXKuCXxvvmqEJjDVamwpPWOW0C_oiryNkazxRe4XW5tSF8d5G3lfa46PC6LXxwKmi82TbG9HRv8NaasndL1k2l8cTafbzcoqta7b2-O88h-nydbibzZLmaLSbPy6QkTJKk1qrQgtKKslLRrCqEVCAlSSnjXAsmlapYSmLMjEte02xc0roaC1CSCcWADdHjyTfm_Gm1D_nOts7ElznNIAKSUxIpcqJKZ713us6Prjko1-UE8r7hvG847xvOzw1HzcNJ02it__EgOE-B_QFKsHbQ</recordid><startdate>202306</startdate><enddate>202306</enddate><creator>Wilhelmi, Florian</creator><creator>Komatsu, Yuji</creator><creator>Yamaguchi, Shinya</creator><creator>Uchida, Yuki</creator><creator>Kase, Tadashi</creator><creator>Kunori, Shinji</creator><creator>Lindemann, Andreas</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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This paper provides a direct evaluation of different assembly strategies for Ga <inline-formula><tex-math notation="LaTeX">_{2}</tex-math></inline-formula> O<inline-formula><tex-math notation="LaTeX">_{3}</tex-math></inline-formula> Schottky diodes. 600Mm thick (current standard) and novel 200 Mm thin large-area diodes are assembled on ceramic substrates in cathode-side cooling (CSC) and junction-side cooling (JSC) configuration, and compared to a commercial SiC reference diode of similar size that was assembled in the same way, which enables a fair comparison. Thermal imaging and measurements of the thermal structure functions reveal the different contributions of die and package to the total thermal resistance. The lowest junction temperature, close to that of the SiC counterpart, is achieved with junction-side cooling. By combining the measurements with thermal simulations, it is shown that an optimization of the die attach thickness or the use of underfill materials in JSC configuration could further lower the average junction temperature and decrease local temperature peaks significantly. The influence of the assembly method, substrate thickness and on-resistance on the power and current rating of the Ga <inline-formula><tex-math notation="LaTeX">_{2}</tex-math></inline-formula> O<inline-formula><tex-math notation="LaTeX">_{3}</tex-math></inline-formula> diodes is discussed for applications where conduction losses dominate.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TPEL.2023.3250026</doi><tpages>11</tpages><orcidid>https://orcid.org/0000-0002-0640-7245</orcidid><orcidid>https://orcid.org/0000-0003-0998-3165</orcidid></addata></record> |
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subjects | Anodes Assembly Conduction losses Configurations Electronic packaging thermal management gallium oxide Gallium oxides Heat transfer Optimization packaging Schottky diodes Side cooling Silicon carbide Substrates Thermal conductivity Thermal imaging Thermal management Thermal resistance Thermal simulation Thickness |
title | Improving the Heat Dissipation and Current Rating of Ga O Schottky Diodes by Substrate Thinning and Junction-Side Cooling |
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