Design parameter optimization for Hall sensor application
A Hall effect sensor using a 7 /spl mu/m, 1.7 /spl Omega/-cm bipolar process was successfully developed. The Hall sensor consists of various patterns, such as regular shapes, rectangles, diamond, hexagon and cross shapes, to optimize offset voltage and sensitivity for proper applications. In order t...
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creator | Chang-Sung Choi Gi-Ho Cha Hyun-Soon Kang Chang-Sup Song |
description | A Hall effect sensor using a 7 /spl mu/m, 1.7 /spl Omega/-cm bipolar process was successfully developed. The Hall sensor consists of various patterns, such as regular shapes, rectangles, diamond, hexagon and cross shapes, to optimize offset voltage and sensitivity for proper applications. In order to measure offset voltage at chip scale, the Agilent 4156C and nano-voltage meter were used and the best structure in offset voltage terms was finally selected by using a ceramic package. The patterns appear to be quadri-rectangular patterns entirely and three-parallelogram patterns. The measured offset voltages were found to be about 173/spl sim/365 /spl mu/V. Meanwhile, in the offset voltage, the standard deviation of the measured values is more important than the average value itself because the unfavorable offset voltages due to mainly misalignment between PISO and N+CONT can be easily overcome by the Hall IC fabrication with compensated processing circuitry. The standard deviation ranges from 78 to 188. The measured misalignment is about 0.32 /spl mu/m. After measuring the offset voltages, we checked the sensitivity by using the Lakeshore electromagnetic field measurement tool. We selected the best patterns for the sensitivity. The measured sensitivities are about 11/spl sim/18 mV/gauss. Furthermore, thermal drift was measured with increasing temperature and the values showed linearity ranging from 0 /spl deg/C to 120 /spl deg/C. |
doi_str_mv | 10.1109/MIEL.2002.1003192 |
format | Conference Proceeding |
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The Hall sensor consists of various patterns, such as regular shapes, rectangles, diamond, hexagon and cross shapes, to optimize offset voltage and sensitivity for proper applications. In order to measure offset voltage at chip scale, the Agilent 4156C and nano-voltage meter were used and the best structure in offset voltage terms was finally selected by using a ceramic package. The patterns appear to be quadri-rectangular patterns entirely and three-parallelogram patterns. The measured offset voltages were found to be about 173/spl sim/365 /spl mu/V. Meanwhile, in the offset voltage, the standard deviation of the measured values is more important than the average value itself because the unfavorable offset voltages due to mainly misalignment between PISO and N+CONT can be easily overcome by the Hall IC fabrication with compensated processing circuitry. The standard deviation ranges from 78 to 188. The measured misalignment is about 0.32 /spl mu/m. After measuring the offset voltages, we checked the sensitivity by using the Lakeshore electromagnetic field measurement tool. We selected the best patterns for the sensitivity. The measured sensitivities are about 11/spl sim/18 mV/gauss. Furthermore, thermal drift was measured with increasing temperature and the values showed linearity ranging from 0 /spl deg/C to 120 /spl deg/C.</description><identifier>ISBN: 0780372352</identifier><identifier>ISBN: 9780780372351</identifier><identifier>DOI: 10.1109/MIEL.2002.1003192</identifier><language>eng</language><publisher>IEEE</publisher><subject>Ceramics ; Chip scale packaging ; Design optimization ; Electromagnetic measurements ; Hall effect devices ; Measurement standards ; Semiconductor device measurement ; Shape ; Temperature measurement ; Voltage measurement</subject><ispartof>2002 23rd International Conference on Microelectronics. Proceedings (Cat. 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No.02TH8595)</title><addtitle>MIEL</addtitle><description>A Hall effect sensor using a 7 /spl mu/m, 1.7 /spl Omega/-cm bipolar process was successfully developed. The Hall sensor consists of various patterns, such as regular shapes, rectangles, diamond, hexagon and cross shapes, to optimize offset voltage and sensitivity for proper applications. In order to measure offset voltage at chip scale, the Agilent 4156C and nano-voltage meter were used and the best structure in offset voltage terms was finally selected by using a ceramic package. The patterns appear to be quadri-rectangular patterns entirely and three-parallelogram patterns. The measured offset voltages were found to be about 173/spl sim/365 /spl mu/V. Meanwhile, in the offset voltage, the standard deviation of the measured values is more important than the average value itself because the unfavorable offset voltages due to mainly misalignment between PISO and N+CONT can be easily overcome by the Hall IC fabrication with compensated processing circuitry. The standard deviation ranges from 78 to 188. The measured misalignment is about 0.32 /spl mu/m. After measuring the offset voltages, we checked the sensitivity by using the Lakeshore electromagnetic field measurement tool. We selected the best patterns for the sensitivity. The measured sensitivities are about 11/spl sim/18 mV/gauss. Furthermore, thermal drift was measured with increasing temperature and the values showed linearity ranging from 0 /spl deg/C to 120 /spl deg/C.</description><subject>Ceramics</subject><subject>Chip scale packaging</subject><subject>Design optimization</subject><subject>Electromagnetic measurements</subject><subject>Hall effect devices</subject><subject>Measurement standards</subject><subject>Semiconductor device measurement</subject><subject>Shape</subject><subject>Temperature measurement</subject><subject>Voltage measurement</subject><isbn>0780372352</isbn><isbn>9780780372351</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2002</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj81Kw0AUhQdEqNY-gLjJCyTeOz_NzFJqtYWIG7sudyY3MpI_Mtno0xu0Z3MOfHA4R4h7hAIR3OPbcV8VEkAWCKDQyStxC6UFVUpl5EpsUvqCRdqglfpGuGdO8bPPRpqo45mnbBjn2MUfmuPQZ80wZQdq2yxxn5ZM49jG8MfuxHVDbeLNxdfi9LL_2B3y6v31uHuq8oilmXM2vq4bYhMUkXe4tU6V6K3jxhqqSxMYA2yN9sY5HZZRYL2i4LWWDhWptXj4743MfB6n2NH0fb68U78BkkW6</recordid><startdate>2002</startdate><enddate>2002</enddate><creator>Chang-Sung Choi</creator><creator>Gi-Ho Cha</creator><creator>Hyun-Soon Kang</creator><creator>Chang-Sup Song</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2002</creationdate><title>Design parameter optimization for Hall sensor application</title><author>Chang-Sung Choi ; Gi-Ho Cha ; Hyun-Soon Kang ; Chang-Sup Song</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-e5bddfae5c3aab91689371b89ef85ad75ce1c0654b5994c82408b3acb442913a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Ceramics</topic><topic>Chip scale packaging</topic><topic>Design optimization</topic><topic>Electromagnetic measurements</topic><topic>Hall effect devices</topic><topic>Measurement standards</topic><topic>Semiconductor device measurement</topic><topic>Shape</topic><topic>Temperature measurement</topic><topic>Voltage measurement</topic><toplevel>online_resources</toplevel><creatorcontrib>Chang-Sung Choi</creatorcontrib><creatorcontrib>Gi-Ho Cha</creatorcontrib><creatorcontrib>Hyun-Soon Kang</creatorcontrib><creatorcontrib>Chang-Sup Song</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chang-Sung Choi</au><au>Gi-Ho Cha</au><au>Hyun-Soon Kang</au><au>Chang-Sup Song</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Design parameter optimization for Hall sensor application</atitle><btitle>2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)</btitle><stitle>MIEL</stitle><date>2002</date><risdate>2002</risdate><volume>1</volume><spage>273</spage><epage>276 vol.1</epage><pages>273-276 vol.1</pages><isbn>0780372352</isbn><isbn>9780780372351</isbn><abstract>A Hall effect sensor using a 7 /spl mu/m, 1.7 /spl Omega/-cm bipolar process was successfully developed. The Hall sensor consists of various patterns, such as regular shapes, rectangles, diamond, hexagon and cross shapes, to optimize offset voltage and sensitivity for proper applications. In order to measure offset voltage at chip scale, the Agilent 4156C and nano-voltage meter were used and the best structure in offset voltage terms was finally selected by using a ceramic package. The patterns appear to be quadri-rectangular patterns entirely and three-parallelogram patterns. The measured offset voltages were found to be about 173/spl sim/365 /spl mu/V. Meanwhile, in the offset voltage, the standard deviation of the measured values is more important than the average value itself because the unfavorable offset voltages due to mainly misalignment between PISO and N+CONT can be easily overcome by the Hall IC fabrication with compensated processing circuitry. The standard deviation ranges from 78 to 188. The measured misalignment is about 0.32 /spl mu/m. After measuring the offset voltages, we checked the sensitivity by using the Lakeshore electromagnetic field measurement tool. We selected the best patterns for the sensitivity. The measured sensitivities are about 11/spl sim/18 mV/gauss. Furthermore, thermal drift was measured with increasing temperature and the values showed linearity ranging from 0 /spl deg/C to 120 /spl deg/C.</abstract><pub>IEEE</pub><doi>10.1109/MIEL.2002.1003192</doi></addata></record> |
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identifier | ISBN: 0780372352 |
ispartof | 2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595), 2002, Vol.1, p.273-276 vol.1 |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Ceramics Chip scale packaging Design optimization Electromagnetic measurements Hall effect devices Measurement standards Semiconductor device measurement Shape Temperature measurement Voltage measurement |
title | Design parameter optimization for Hall sensor application |
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