A Robust Forward Compensated Type-2 PLL without DC Phase Error During Frequency Ramp for Embedded Magnetic Encoder
To achieve high performance vector control of permanent magnet synchronous machine (PMSM), high precision rotor angle is essential. Compared to traditionally used angle feedback device, e.g., encoder and resolver, the embedded magnetic encoder (EME) achieves high precision angle estimation without e...
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Veröffentlicht in: | IEEE transactions on power electronics 2023-05, Vol.38 (5), p.1-5 |
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description | To achieve high performance vector control of permanent magnet synchronous machine (PMSM), high precision rotor angle is essential. Compared to traditionally used angle feedback device, e.g., encoder and resolver, the embedded magnetic encoder (EME) achieves high precision angle estimation without extra space occupation by installing several linear Hall sensors into PMSM cavity to monitor the flux leakage and rotor angle. The conventional synchronous reference frame (SRF) phase-locked loop (PLL) can extract phase and frequency from three or two Hall signals simultaneously. Although the type-2 SRF-PLL shows good robust performance against parameter variation, phase error emerges when input frequency changes. More specifically, a DC phase error appears in type-2 SRF-PLL during speed ramp stage due to insufficient order. Increase of the loop order removes the DC phase error but leads to instability risk. In this paper, a novel forward compensation (FC) module is attached on type-2 SRF-PLL to achieve phase error-free when frequency changes, where the instability risk is avoided. The effectiveness of proposed FC module is analytically and experimentally proved, where the phase error elimination, noise immunity and dynamic response are evaluated. |
doi_str_mv | 10.1109/TPEL.2023.3239362 |
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Compared to traditionally used angle feedback device, e.g., encoder and resolver, the embedded magnetic encoder (EME) achieves high precision angle estimation without extra space occupation by installing several linear Hall sensors into PMSM cavity to monitor the flux leakage and rotor angle. The conventional synchronous reference frame (SRF) phase-locked loop (PLL) can extract phase and frequency from three or two Hall signals simultaneously. Although the type-2 SRF-PLL shows good robust performance against parameter variation, phase error emerges when input frequency changes. More specifically, a DC phase error appears in type-2 SRF-PLL during speed ramp stage due to insufficient order. Increase of the loop order removes the DC phase error but leads to instability risk. In this paper, a novel forward compensation (FC) module is attached on type-2 SRF-PLL to achieve phase error-free when frequency changes, where the instability risk is avoided. The effectiveness of proposed FC module is analytically and experimentally proved, where the phase error elimination, noise immunity and dynamic response are evaluated.</description><identifier>ISSN: 0885-8993</identifier><identifier>EISSN: 1941-0107</identifier><identifier>DOI: 10.1109/TPEL.2023.3239362</identifier><identifier>CODEN: ITPEE8</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Coders ; DC phase error ; Dynamic response ; Embedded magnetic encoder ; forward compensation ; Frequency synchronization ; Hall effect ; Magnetic separation ; Mathematical analysis ; Modules ; Parameter robustness ; Permanent magnets ; Phase error ; Phase locked loops ; phase-locked loop ; Power electronics ; Resolvers ; Robustness ; Rotors ; stability ; Steady-state ; Synchronous machines ; Voltage-controlled oscillators</subject><ispartof>IEEE transactions on power electronics, 2023-05, Vol.38 (5), p.1-5</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2023</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c294t-9e993e1dafcb8360a970beb0d591ec9bb7be7803d551b930597f08bb9e6b2a613</citedby><cites>FETCH-LOGICAL-c294t-9e993e1dafcb8360a970beb0d591ec9bb7be7803d551b930597f08bb9e6b2a613</cites><orcidid>0000-0003-2625-6752 ; 0000-0002-2047-9712 ; 0000-0002-6439-5502</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10024974$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10024974$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Wang, Yuchen</creatorcontrib><creatorcontrib>Zhang, Hengliang</creatorcontrib><creatorcontrib>Hua, Wei</creatorcontrib><title>A Robust Forward Compensated Type-2 PLL without DC Phase Error During Frequency Ramp for Embedded Magnetic Encoder</title><title>IEEE transactions on power electronics</title><addtitle>TPEL</addtitle><description>To achieve high performance vector control of permanent magnet synchronous machine (PMSM), high precision rotor angle is essential. Compared to traditionally used angle feedback device, e.g., encoder and resolver, the embedded magnetic encoder (EME) achieves high precision angle estimation without extra space occupation by installing several linear Hall sensors into PMSM cavity to monitor the flux leakage and rotor angle. The conventional synchronous reference frame (SRF) phase-locked loop (PLL) can extract phase and frequency from three or two Hall signals simultaneously. Although the type-2 SRF-PLL shows good robust performance against parameter variation, phase error emerges when input frequency changes. More specifically, a DC phase error appears in type-2 SRF-PLL during speed ramp stage due to insufficient order. Increase of the loop order removes the DC phase error but leads to instability risk. In this paper, a novel forward compensation (FC) module is attached on type-2 SRF-PLL to achieve phase error-free when frequency changes, where the instability risk is avoided. The effectiveness of proposed FC module is analytically and experimentally proved, where the phase error elimination, noise immunity and dynamic response are evaluated.</description><subject>Coders</subject><subject>DC phase error</subject><subject>Dynamic response</subject><subject>Embedded magnetic encoder</subject><subject>forward compensation</subject><subject>Frequency synchronization</subject><subject>Hall effect</subject><subject>Magnetic separation</subject><subject>Mathematical analysis</subject><subject>Modules</subject><subject>Parameter robustness</subject><subject>Permanent magnets</subject><subject>Phase error</subject><subject>Phase locked loops</subject><subject>phase-locked loop</subject><subject>Power electronics</subject><subject>Resolvers</subject><subject>Robustness</subject><subject>Rotors</subject><subject>stability</subject><subject>Steady-state</subject><subject>Synchronous machines</subject><subject>Voltage-controlled oscillators</subject><issn>0885-8993</issn><issn>1941-0107</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkF1LwzAUhoMoOKc_QPAi4HXnSdKvXI7ZqVBxjHkdkvZ067BNTVrG_r0d24VX5-L9OC8PIY8MZoyBfNmssnzGgYuZ4EKKmF-RCZMhC4BBck0mkKZRkEopbsmd93sAFkbAJsTN6dqawfd0ad1Bu5IubNNh63WPJd0cOww4XeU5PdT9zg49fV3Q1U57pJlz1tHXwdXtli4d_g7YFke61k1Hq1HJGoNlOZZ86m2LfV3QrC1sie6e3FT6x-PD5U7J9zLbLN6D_OvtYzHPg4LLsA8kjmuRlboqTCpi0DIBgwbKSDIspDGJwSQFUUYRM1JAJJMKUmMkxobrmIkpeT73ds6O43yv9nZw7fhS8SSNZSJSGY8udnYVznrvsFKdqxvtjoqBOqFVJ7TqhFZd0I6Zp3OmRsR_fuChTELxB0FCdNA</recordid><startdate>20230501</startdate><enddate>20230501</enddate><creator>Wang, Yuchen</creator><creator>Zhang, Hengliang</creator><creator>Hua, Wei</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7TB</scope><scope>8FD</scope><scope>FR3</scope><scope>JQ2</scope><scope>KR7</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-2625-6752</orcidid><orcidid>https://orcid.org/0000-0002-2047-9712</orcidid><orcidid>https://orcid.org/0000-0002-6439-5502</orcidid></search><sort><creationdate>20230501</creationdate><title>A Robust Forward Compensated Type-2 PLL without DC Phase Error During Frequency Ramp for Embedded Magnetic Encoder</title><author>Wang, Yuchen ; Zhang, Hengliang ; Hua, Wei</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c294t-9e993e1dafcb8360a970beb0d591ec9bb7be7803d551b930597f08bb9e6b2a613</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2023</creationdate><topic>Coders</topic><topic>DC phase error</topic><topic>Dynamic response</topic><topic>Embedded magnetic encoder</topic><topic>forward compensation</topic><topic>Frequency synchronization</topic><topic>Hall effect</topic><topic>Magnetic separation</topic><topic>Mathematical analysis</topic><topic>Modules</topic><topic>Parameter robustness</topic><topic>Permanent magnets</topic><topic>Phase error</topic><topic>Phase locked loops</topic><topic>phase-locked loop</topic><topic>Power electronics</topic><topic>Resolvers</topic><topic>Robustness</topic><topic>Rotors</topic><topic>stability</topic><topic>Steady-state</topic><topic>Synchronous machines</topic><topic>Voltage-controlled oscillators</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Wang, Yuchen</creatorcontrib><creatorcontrib>Zhang, Hengliang</creatorcontrib><creatorcontrib>Hua, Wei</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Technology Research Database</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Civil Engineering Abstracts</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on power electronics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Wang, Yuchen</au><au>Zhang, Hengliang</au><au>Hua, Wei</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Robust Forward Compensated Type-2 PLL without DC Phase Error During Frequency Ramp for Embedded Magnetic Encoder</atitle><jtitle>IEEE transactions on power electronics</jtitle><stitle>TPEL</stitle><date>2023-05-01</date><risdate>2023</risdate><volume>38</volume><issue>5</issue><spage>1</spage><epage>5</epage><pages>1-5</pages><issn>0885-8993</issn><eissn>1941-0107</eissn><coden>ITPEE8</coden><abstract>To achieve high performance vector control of permanent magnet synchronous machine (PMSM), high precision rotor angle is essential. Compared to traditionally used angle feedback device, e.g., encoder and resolver, the embedded magnetic encoder (EME) achieves high precision angle estimation without extra space occupation by installing several linear Hall sensors into PMSM cavity to monitor the flux leakage and rotor angle. The conventional synchronous reference frame (SRF) phase-locked loop (PLL) can extract phase and frequency from three or two Hall signals simultaneously. Although the type-2 SRF-PLL shows good robust performance against parameter variation, phase error emerges when input frequency changes. More specifically, a DC phase error appears in type-2 SRF-PLL during speed ramp stage due to insufficient order. Increase of the loop order removes the DC phase error but leads to instability risk. In this paper, a novel forward compensation (FC) module is attached on type-2 SRF-PLL to achieve phase error-free when frequency changes, where the instability risk is avoided. The effectiveness of proposed FC module is analytically and experimentally proved, where the phase error elimination, noise immunity and dynamic response are evaluated.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TPEL.2023.3239362</doi><tpages>5</tpages><orcidid>https://orcid.org/0000-0003-2625-6752</orcidid><orcidid>https://orcid.org/0000-0002-2047-9712</orcidid><orcidid>https://orcid.org/0000-0002-6439-5502</orcidid></addata></record> |
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subjects | Coders DC phase error Dynamic response Embedded magnetic encoder forward compensation Frequency synchronization Hall effect Magnetic separation Mathematical analysis Modules Parameter robustness Permanent magnets Phase error Phase locked loops phase-locked loop Power electronics Resolvers Robustness Rotors stability Steady-state Synchronous machines Voltage-controlled oscillators |
title | A Robust Forward Compensated Type-2 PLL without DC Phase Error During Frequency Ramp for Embedded Magnetic Encoder |
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