Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system / Victor A. Carreno, G. Choi and R.K. Iyer
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| creator | Carreno, Victor A |
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| identifier | OCLC: 22778293 |
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| language | eng |
| recordid | cdi_hathitrust_hathifiles_uiug_30112106567479 |
| source | HathiTrust Digital Library Full View Worldwide |
| title | Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system / Victor A. Carreno, G. Choi and R.K. Iyer |
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