Low-power SRAMs power mode control logic: Failure analysis and test solutions
Low-power SRAMs embed power gating mechanisms for reducing static power consumption. Power gating is implemented through power switches for controlling the supply voltage applied to the various memory blocks (array, decoders, I/O logic, etc.). This way, one or more memory blocks can be disconnected...
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| creator | Zordan, L. B. Bosio, A. Dilillo, L. Girard, P. Todri, A. Virazel, A. Badereddine, N. |
| description | Low-power SRAMs embed power gating mechanisms for reducing static power consumption. Power gating is implemented through power switches for controlling the supply voltage applied to the various memory blocks (array, decoders, I/O logic, etc.). This way, one or more memory blocks can be disconnected from the power supply during a long period of inactivity, thus reducing static power consumption. This paper focuses on low-power SRAMs, and in particular, the power gating mechanisms of core-cells and peripheral circuitry. We provide a detailed analysis based on electrical simulations to characterize the impact of resistive-open defects on the power mode control logic. Based on this analysis, we introduce appropriate fault models that represent the observed faulty behaviors. Finally, we propose an efficient test solution targeting the set of identified fault models. |
| doi_str_mv | 10.1109/TEST.2012.6401578 |
| format | Conference Proceeding |
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B.</creatorcontrib><creatorcontrib>Bosio, A.</creatorcontrib><creatorcontrib>Dilillo, L.</creatorcontrib><creatorcontrib>Girard, P.</creatorcontrib><creatorcontrib>Todri, A.</creatorcontrib><creatorcontrib>Virazel, A.</creatorcontrib><creatorcontrib>Badereddine, N.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection><collection>Hyper Article en Ligne (HAL)</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zordan, L. B.</au><au>Bosio, A.</au><au>Dilillo, L.</au><au>Girard, P.</au><au>Todri, A.</au><au>Virazel, A.</au><au>Badereddine, N.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Low-power SRAMs power mode control logic: Failure analysis and test solutions</atitle><btitle>2012 IEEE International Test Conference</btitle><stitle>TEST</stitle><date>2012-11</date><risdate>2012</risdate><spage>1</spage><epage>10</epage><pages>1-10</pages><issn>1089-3539</issn><eissn>2378-2250</eissn><isbn>146731594X</isbn><isbn>9781467315944</isbn><eisbn>9781467315951</eisbn><eisbn>9781467315937</eisbn><eisbn>1467315931</eisbn><eisbn>1467315958</eisbn><abstract>Low-power SRAMs embed power gating mechanisms for reducing static power consumption. Power gating is implemented through power switches for controlling the supply voltage applied to the various memory blocks (array, decoders, I/O logic, etc.). This way, one or more memory blocks can be disconnected from the power supply during a long period of inactivity, thus reducing static power consumption. This paper focuses on low-power SRAMs, and in particular, the power gating mechanisms of core-cells and peripheral circuitry. We provide a detailed analysis based on electrical simulations to characterize the impact of resistive-open defects on the power mode control logic. Based on this analysis, we introduce appropriate fault models that represent the observed faulty behaviors. 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| identifier | ISSN: 1089-3539 |
| ispartof | 2012 IEEE International Test Conference, 2012, p.1-10 |
| issn | 1089-3539 2378-2250 |
| language | eng |
| recordid | cdi_hal_primary_oai_HAL_lirmm_00805143v1 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Arrays Circuit faults Delay Electronics Engineering Sciences MOSFETs Random access memory Voltage control |
| title | Low-power SRAMs power mode control logic: Failure analysis and test solutions |
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