Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR

•TCAD transient simulation for Single Photon Avalanche Diodes integrated in 28 nm FD-SOI CMOS technology.•Unexpected behavior of the reference SPAD structure.•Various approaches to improve SPAD FD-SOI behavior.•Dark Count Rate improvement with optimizations of the SPAD structure. This article presen...

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Veröffentlicht in:	Solid-state electronics 2022-05, Vol.191, p.108297, Article 108297
Hauptverfasser:	Issartel, D., Gao, S., Pittet, P., Cellier, R., Golanski, D., Cathelin, A., Calmon, F.
Format:	Artikel
Sprache:	eng
Schlagworte:	Avalanche process Dark Count Rate – DCR Engineering Sciences FD-SOI CMOS Micro and nanotechnologies Microelectronics Shallow Trench isolation – STI SPAD TCAD simulation
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