Extraction of the Parasitic Bipolar Gain Using the Back-Gate in Ultrathin FD SOI MOSFETs
We propose a new method to extract the gain of the parasitic bipolar transistor in ultrathin fully-depleted silicon-on-insulator MOSFETs. The method is based on the modulation of the parasitic bipolar effect by back-gate biasing. The bipolar gain can be determined for each transistor, without the ne...
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| Veröffentlicht in: | IEEE electron device letters 2015-02, Vol.36 (2), p.96-98 |
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| container_end_page | 98 |
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| container_issue | 2 |
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| container_title | IEEE electron device letters |
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| creator | Fanyu Liu Ionica, Irina Bawedin, Maryline Cristoloveanu, Sorin |
| description | We propose a new method to extract the gain of the parasitic bipolar transistor in ultrathin fully-depleted silicon-on-insulator MOSFETs. The method is based on the modulation of the parasitic bipolar effect by back-gate biasing. The bipolar gain can be determined for each transistor, without the need to compare the long and short devices. The proposed method is validated by experimental data and numerical simulations. |
| doi_str_mv | 10.1109/LED.2014.2385797 |
| format | Article |
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The method is based on the modulation of the parasitic bipolar effect by back-gate biasing. The bipolar gain can be determined for each transistor, without the need to compare the long and short devices. The proposed method is validated by experimental data and numerical simulations.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2014.2385797</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>IEEE</publisher><subject>back gate ; band-to-band tunneling ; Current measurement ; Engineering Sciences ; Junctions ; Leakage currents ; Logic gates ; Micro and nanotechnologies ; Microelectronics ; MOSFET ; parasitic bipolar effect ; Tunneling ; ultra-thin FD SOI ; Voltage measurement</subject><ispartof>IEEE electron device letters, 2015-02, Vol.36 (2), p.96-98</ispartof><rights>Distributed under a Creative Commons Attribution 4.0 International License</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c297t-b06dfbf57c067f434bf1490f9e16801a62fc79d16c6a9796f6987043d6d4e4a73</citedby><cites>FETCH-LOGICAL-c297t-b06dfbf57c067f434bf1490f9e16801a62fc79d16c6a9796f6987043d6d4e4a73</cites><orcidid>0000-0002-9412-6581 ; 0000-0002-3576-5586</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6998036$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>230,314,780,784,796,885,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6998036$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttps://hal.science/hal-02004030$$DView record in HAL$$Hfree_for_read</backlink></links><search><creatorcontrib>Fanyu Liu</creatorcontrib><creatorcontrib>Ionica, Irina</creatorcontrib><creatorcontrib>Bawedin, Maryline</creatorcontrib><creatorcontrib>Cristoloveanu, Sorin</creatorcontrib><title>Extraction of the Parasitic Bipolar Gain Using the Back-Gate in Ultrathin FD SOI MOSFETs</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>We propose a new method to extract the gain of the parasitic bipolar transistor in ultrathin fully-depleted silicon-on-insulator MOSFETs. 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The proposed method is validated by experimental data and numerical simulations.</description><subject>back gate</subject><subject>band-to-band tunneling</subject><subject>Current measurement</subject><subject>Engineering Sciences</subject><subject>Junctions</subject><subject>Leakage currents</subject><subject>Logic gates</subject><subject>Micro and nanotechnologies</subject><subject>Microelectronics</subject><subject>MOSFET</subject><subject>parasitic bipolar effect</subject><subject>Tunneling</subject><subject>ultra-thin FD SOI</subject><subject>Voltage measurement</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2015</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM1LwzAYh4MoOKd3wUuuHjrfNGnSHPe9QWXCHHgLWZq4aF1HE0T_e1s3dsrLj-fJ4UHonsCAEJBPxXQySIGwQUrzTEhxgXoky_IEMk4vUQ8EIwklwK_RTQgf0JJMsB56m_7ERpvo6z2uHY47i190o4OP3uCRP9SVbvBc-z3eBL9__wdG2nwmcx0t7uaq9eOuvWYTvF4t8fNqPZu-hlt05XQV7N3p7aNNO48XSbGaL8fDIjGpFDHZAi_d1mXCABeOUbZ1hElw0hKeA9E8dUbIknDDtRSSOy5zAYyWvGSWaUH76PH4705X6tD4L938qlp7tRgWqtsgBWBA4Zu0LBxZ09QhNNadBQKqq6jaiqqrqE4VW-XhqHhr7RnnUuZAOf0DTelq-Q</recordid><startdate>201502</startdate><enddate>201502</enddate><creator>Fanyu Liu</creator><creator>Ionica, Irina</creator><creator>Bawedin, Maryline</creator><creator>Cristoloveanu, Sorin</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>1XC</scope><orcidid>https://orcid.org/0000-0002-9412-6581</orcidid><orcidid>https://orcid.org/0000-0002-3576-5586</orcidid></search><sort><creationdate>201502</creationdate><title>Extraction of the Parasitic Bipolar Gain Using the Back-Gate in Ultrathin FD SOI MOSFETs</title><author>Fanyu Liu ; Ionica, Irina ; Bawedin, Maryline ; Cristoloveanu, Sorin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c297t-b06dfbf57c067f434bf1490f9e16801a62fc79d16c6a9796f6987043d6d4e4a73</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2015</creationdate><topic>back gate</topic><topic>band-to-band tunneling</topic><topic>Current measurement</topic><topic>Engineering Sciences</topic><topic>Junctions</topic><topic>Leakage currents</topic><topic>Logic gates</topic><topic>Micro and nanotechnologies</topic><topic>Microelectronics</topic><topic>MOSFET</topic><topic>parasitic bipolar effect</topic><topic>Tunneling</topic><topic>ultra-thin FD SOI</topic><topic>Voltage measurement</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Fanyu Liu</creatorcontrib><creatorcontrib>Ionica, Irina</creatorcontrib><creatorcontrib>Bawedin, Maryline</creatorcontrib><creatorcontrib>Cristoloveanu, Sorin</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Hyper Article en Ligne (HAL)</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Fanyu Liu</au><au>Ionica, Irina</au><au>Bawedin, Maryline</au><au>Cristoloveanu, Sorin</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Extraction of the Parasitic Bipolar Gain Using the Back-Gate in Ultrathin FD SOI MOSFETs</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2015-02</date><risdate>2015</risdate><volume>36</volume><issue>2</issue><spage>96</spage><epage>98</epage><pages>96-98</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>We propose a new method to extract the gain of the parasitic bipolar transistor in ultrathin fully-depleted silicon-on-insulator MOSFETs. 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| ispartof | IEEE electron device letters, 2015-02, Vol.36 (2), p.96-98 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | back gate band-to-band tunneling Current measurement Engineering Sciences Junctions Leakage currents Logic gates Micro and nanotechnologies Microelectronics MOSFET parasitic bipolar effect Tunneling ultra-thin FD SOI Voltage measurement |
| title | Extraction of the Parasitic Bipolar Gain Using the Back-Gate in Ultrathin FD SOI MOSFETs |
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