Study of an embedded buried SiGe structure as a mobility booster for fully-depleted SOI MOSFETs at the 10nm node
This paper presents mechanical simulations results of an innovative strain transfer structure consisting in a buried compressive SiGe layer embedded under an ultra-thin buried oxide (BOX). We studied the influence of different dimensions including the active area and determined optimal parameters of...
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Veröffentlicht in: | Solid-state electronics 2014-08, Vol.98, p.50-54 |
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creator | Morvan, S. Andrieu, F. Barbé, J.-C. Ghibaudo, G. |
description | This paper presents mechanical simulations results of an innovative strain transfer structure consisting in a buried compressive SiGe layer embedded under an ultra-thin buried oxide (BOX). We studied the influence of different dimensions including the active area and determined optimal parameters of the SiGe layer maximizing the strain. We demonstrate a transfer of a tensile stress up to 1.3GPa in the silicon. Thanks to 3D simulations and the study of stress profiles in the SOI, the electron mobility enhancement is estimated to be about 80% for logic transistors at the 10nm node. The strain induced in the channel by the edge relaxation of an embedded buried SiGe layer is compared to strained Silicon-On-Insulator (sSOI) wafers and strained nitride layer for Fully Depleted Silicon-On-Insulator (FDSOI). |
doi_str_mv | 10.1016/j.sse.2014.04.013 |
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We studied the influence of different dimensions including the active area and determined optimal parameters of the SiGe layer maximizing the strain. We demonstrate a transfer of a tensile stress up to 1.3GPa in the silicon. Thanks to 3D simulations and the study of stress profiles in the SOI, the electron mobility enhancement is estimated to be about 80% for logic transistors at the 10nm node. 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We studied the influence of different dimensions including the active area and determined optimal parameters of the SiGe layer maximizing the strain. We demonstrate a transfer of a tensile stress up to 1.3GPa in the silicon. Thanks to 3D simulations and the study of stress profiles in the SOI, the electron mobility enhancement is estimated to be about 80% for logic transistors at the 10nm node. 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subjects | Embedded buried SiGe Engineering Sciences FDSOI Micro and nanotechnologies Microelectronics sSOI Strain transfer |
title | Study of an embedded buried SiGe structure as a mobility booster for fully-depleted SOI MOSFETs at the 10nm node |
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