On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures

This paper addresses the important issue of fault tolerance in network-on-chip (NoC) and presents an on-the-field test and configuration infrastructure for a 2-D-mesh NoC, which can be used in many generic shared-memory many-core tiled architectures and MPSoCs. This paper also details all the hardwa...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2014-06, Vol.22 (6), p.1364-1376
Hauptverfasser:	Zhen Zhang, Refauvelet, Dimitri, Greiner, Alain, Benabdenbi, Mounir, Pecheux, Francois
Format:	Artikel
Sprache:	eng
Schlagworte:	Built-in self-test Built-in self-test (BIST) Circuit faults Computer architecture Engineering Sciences fault tolerance Hardware many cores Micro and nanotechnologies Microelectronics network-on-chip (NoC) reconfiguration Routing Silicon test Topology
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