Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

► Low RESURF effectiveness found in conventional P-channel LDMOS on thin-SOI. ► NBL layer is inserted in the drift region by high energy implantation. ► Significant improvement of static performance in the proposed LDPMOS. ► Further improvement is observed by using STI partially covering the drift region. This paper analyses the experimental results of voltage capability (VBR>120V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.