Highly controllable dual-gate microcrystalline silicon thin film transistor processed at low temperature ( T < 180 °C)
► We fabricated dual-gate microcrystalline silicon TFTs at very low temperature ( T < 180 °C). ► We demonstrated a very efficient control of the threshold voltage V TH. ► The coupling coefficient can be compared to the usual values of fully depleted SOI FETs. ► The high efficiency is mainly due t...
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| creator | Kandoussi, K. Jacques, E. Coulon, N. Simon, C. Mohammed-Brahim, T. |
| description | ► We fabricated dual-gate microcrystalline silicon TFTs at very low temperature (
T
<
180
°C). ► We demonstrated a very efficient control of the threshold voltage
V
TH. ► The coupling coefficient can be compared to the usual values of fully depleted SOI FETs. ► The high efficiency is mainly due to the use of very thin film and to its electrical quality.
The addition of a top-gate to a bottom gate microcrystalline silicon thin film transistor (TFT) that is processed at a maximum temperature of 180
°C, is shown to lead to a very efficient control of the threshold voltage
V
TH. A real time control of CMOS pairing is then possible. The value of the coupling coefficient that is the ratio of the variation of
V
TH on the variation of the voltage of the top-gate control is 0.7. This efficient control is mainly due to the use of very thin, 50
nm thick, active layer and to its electrical quality that leads to a full depletion. |
| doi_str_mv | 10.1016/j.sse.2011.05.015 |
| format | Article |
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T
<
180
°C). ► We demonstrated a very efficient control of the threshold voltage
V
TH. ► The coupling coefficient can be compared to the usual values of fully depleted SOI FETs. ► The high efficiency is mainly due to the use of very thin film and to its electrical quality.
The addition of a top-gate to a bottom gate microcrystalline silicon thin film transistor (TFT) that is processed at a maximum temperature of 180
°C, is shown to lead to a very efficient control of the threshold voltage
V
TH. A real time control of CMOS pairing is then possible. The value of the coupling coefficient that is the ratio of the variation of
V
TH on the variation of the voltage of the top-gate control is 0.7. This efficient control is mainly due to the use of very thin, 50
nm thick, active layer and to its electrical quality that leads to a full depletion.</description><identifier>ISSN: 0038-1101</identifier><identifier>EISSN: 1879-2405</identifier><identifier>DOI: 10.1016/j.sse.2011.05.015</identifier><language>eng</language><publisher>Kidlington: Elsevier Ltd</publisher><subject>Applied sciences ; CMOS ; CMOS electronics ; Design. Technologies. Operation analysis. Testing ; DG-TFT ; Electric potential ; Electronics ; Exact sciences and technology ; Integrated circuits ; Low temperature substrate ; Microcrystalline silicon ; Semiconductor devices ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Silicon films ; Thin films ; Transistors ; Voltage</subject><ispartof>Solid-state electronics, 2011-09, Vol.63 (1), p.140-144</ispartof><rights>2011 Elsevier Ltd</rights><rights>2015 INIST-CNRS</rights><rights>Distributed under a Creative Commons Attribution 4.0 International License</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c436t-9678aa6738ff23e25557f072f66ffdc1475b39c4723e2b526fb88030f0d686093</citedby><cites>FETCH-LOGICAL-c436t-9678aa6738ff23e25557f072f66ffdc1475b39c4723e2b526fb88030f0d686093</cites><orcidid>0000-0002-2807-6811</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://www.sciencedirect.com/science/article/pii/S0038110111001900$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>230,314,776,780,881,3537,27901,27902,65306</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=24480368$$DView record in Pascal Francis$$Hfree_for_read</backlink><backlink>$$Uhttps://hal.science/hal-00905327$$DView record in HAL$$Hfree_for_read</backlink></links><search><creatorcontrib>Kandoussi, K.</creatorcontrib><creatorcontrib>Jacques, E.</creatorcontrib><creatorcontrib>Coulon, N.</creatorcontrib><creatorcontrib>Simon, C.</creatorcontrib><creatorcontrib>Mohammed-Brahim, T.</creatorcontrib><title>Highly controllable dual-gate microcrystalline silicon thin film transistor processed at low temperature ( T < 180 °C)</title><title>Solid-state electronics</title><description>► We fabricated dual-gate microcrystalline silicon TFTs at very low temperature (
T
<
180
°C). ► We demonstrated a very efficient control of the threshold voltage
V
TH. ► The coupling coefficient can be compared to the usual values of fully depleted SOI FETs. ► The high efficiency is mainly due to the use of very thin film and to its electrical quality.
The addition of a top-gate to a bottom gate microcrystalline silicon thin film transistor (TFT) that is processed at a maximum temperature of 180
°C, is shown to lead to a very efficient control of the threshold voltage
V
TH. A real time control of CMOS pairing is then possible. The value of the coupling coefficient that is the ratio of the variation of
V
TH on the variation of the voltage of the top-gate control is 0.7. This efficient control is mainly due to the use of very thin, 50
nm thick, active layer and to its electrical quality that leads to a full depletion.</description><subject>Applied sciences</subject><subject>CMOS</subject><subject>CMOS electronics</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>DG-TFT</subject><subject>Electric potential</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Low temperature substrate</subject><subject>Microcrystalline silicon</subject><subject>Semiconductor devices</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Silicon films</subject><subject>Thin films</subject><subject>Transistors</subject><subject>Voltage</subject><issn>0038-1101</issn><issn>1879-2405</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><recordid>eNp9kcFuEzEQhlcVSA0tD8DNFwQ97HZsr71ewaWKgCBF4lLOluMdN468u8F2WuWt-gw8GY5S9chpJM83_4z_v6o-UGgoUHm7a1LChgGlDYgGqLioFlR1fc1aEG-qBQBXNS3oZfUupR0AMElhUT2t_MM2HImdpxznEMwmIBkOJtQPJiMZvY2zjceUTQh-QpJ88IUleesn4nwYSY5mSj7lOZJ9YbHcMRCTSZifSMZxj9HkQ0TymdyTr4QqIH-flzfX1VtnQsL3L_Wq-v392_1yVa9__fi5vFvXtuUy173slDGy48o5xpEJIToHHXNSOjdY2nZiw3vbdqfmRjDpNkoBBweDVBJ6flXdnHW3Juh99KOJRz0br1d3a316A-hBcNY90sJ-OrPlH38OmLIefbJYTJlwPiTd077nbdleSHomizspRXSv0hT0KQ-908UHfcpDg9AljzLz8UXdJGuCK7ZZn14HWduWw6Uq3Jczh8WWR49RJ-txsjj4iDbrYfb_2fIP0LefcA</recordid><startdate>20110901</startdate><enddate>20110901</enddate><creator>Kandoussi, K.</creator><creator>Jacques, E.</creator><creator>Coulon, N.</creator><creator>Simon, C.</creator><creator>Mohammed-Brahim, T.</creator><general>Elsevier Ltd</general><general>Elsevier</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope><scope>1XC</scope><orcidid>https://orcid.org/0000-0002-2807-6811</orcidid></search><sort><creationdate>20110901</creationdate><title>Highly controllable dual-gate microcrystalline silicon thin film transistor processed at low temperature ( T < 180 °C)</title><author>Kandoussi, K. ; Jacques, E. ; Coulon, N. ; Simon, C. ; Mohammed-Brahim, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c436t-9678aa6738ff23e25557f072f66ffdc1475b39c4723e2b526fb88030f0d686093</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Applied sciences</topic><topic>CMOS</topic><topic>CMOS electronics</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>DG-TFT</topic><topic>Electric potential</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Low temperature substrate</topic><topic>Microcrystalline silicon</topic><topic>Semiconductor devices</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Silicon films</topic><topic>Thin films</topic><topic>Transistors</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kandoussi, K.</creatorcontrib><creatorcontrib>Jacques, E.</creatorcontrib><creatorcontrib>Coulon, N.</creatorcontrib><creatorcontrib>Simon, C.</creatorcontrib><creatorcontrib>Mohammed-Brahim, T.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Hyper Article en Ligne (HAL)</collection><jtitle>Solid-state electronics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Kandoussi, K.</au><au>Jacques, E.</au><au>Coulon, N.</au><au>Simon, C.</au><au>Mohammed-Brahim, T.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Highly controllable dual-gate microcrystalline silicon thin film transistor processed at low temperature ( T < 180 °C)</atitle><jtitle>Solid-state electronics</jtitle><date>2011-09-01</date><risdate>2011</risdate><volume>63</volume><issue>1</issue><spage>140</spage><epage>144</epage><pages>140-144</pages><issn>0038-1101</issn><eissn>1879-2405</eissn><abstract>► We fabricated dual-gate microcrystalline silicon TFTs at very low temperature (
T
<
180
°C). ► We demonstrated a very efficient control of the threshold voltage
V
TH. ► The coupling coefficient can be compared to the usual values of fully depleted SOI FETs. ► The high efficiency is mainly due to the use of very thin film and to its electrical quality.
The addition of a top-gate to a bottom gate microcrystalline silicon thin film transistor (TFT) that is processed at a maximum temperature of 180
°C, is shown to lead to a very efficient control of the threshold voltage
V
TH. A real time control of CMOS pairing is then possible. The value of the coupling coefficient that is the ratio of the variation of
V
TH on the variation of the voltage of the top-gate control is 0.7. This efficient control is mainly due to the use of very thin, 50
nm thick, active layer and to its electrical quality that leads to a full depletion.</abstract><cop>Kidlington</cop><pub>Elsevier Ltd</pub><doi>10.1016/j.sse.2011.05.015</doi><tpages>5</tpages><orcidid>https://orcid.org/0000-0002-2807-6811</orcidid><oa>free_for_read</oa></addata></record> |
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| ispartof | Solid-state electronics, 2011-09, Vol.63 (1), p.140-144 |
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| language | eng |
| recordid | cdi_hal_primary_oai_HAL_hal_00905327v1 |
| source | Elsevier ScienceDirect Journals |
| subjects | Applied sciences CMOS CMOS electronics Design. Technologies. Operation analysis. Testing DG-TFT Electric potential Electronics Exact sciences and technology Integrated circuits Low temperature substrate Microcrystalline silicon Semiconductor devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon films Thin films Transistors Voltage |
| title | Highly controllable dual-gate microcrystalline silicon thin film transistor processed at low temperature ( T < 180 °C) |
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