An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing
A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image pr...
Gespeichert in:
| Veröffentlicht in: | EURASIP journal on embedded systems 2009-01, Vol.2008 (1), p.961315, Article 961315 |
|---|---|
| Hauptverfasser: | , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | 1 |
| container_start_page | 961315 |
| container_title | EURASIP journal on embedded systems |
| container_volume | 2008 |
| creator | Ginhac, Dominique Dubois, Jérôme Paindavoine, Michel Heyrman, Barthélémy |
| description | A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators are implemented on the circuit. Each pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A
pixel proof-of-concept chip was fabricated in a 0.35
m standard CMOS process, with a pixel size of 35
m
35
m. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. The chip can capture raw images up to 10 000 frames per second and runs low-level image processing at a framerate of 2 000 to 5 000 frames per second. |
| doi_str_mv | 10.1155/2008/961315 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_hal_p</sourceid><recordid>TN_cdi_hal_primary_oai_HAL_hal_00517911v1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2806657298</sourcerecordid><originalsourceid>FETCH-LOGICAL-c427t-bf1e723341eb33c2ef3b50970d8fc8971a44a17f5b6bb423d362e61b58049e043</originalsourceid><addsrcrecordid>eNp10VtLwzAUB_AiCl6f_AJBQRCty8m9j2NeNpg48PIa0i7tIr3MZFP89rZUVESfEsIvJ-fkH0WHgC8AOB8QjNUgEUCBb0Q7IJSMaSLo5o_9drQbwjPGTCiqdqLbYY3uJ7eXaOabwpuqMmlp0ZMLrqnRaOGW6M2tFmjsikV8v7R2jq6bzJRoVpraokllCttdzWwIri72o63clMEefK570eP11cNoHE_vbiaj4TTOGJGrOM3BSkIpA5tSmhGb05TjROK5yjOVSDCMGZA5T0WaMkLnVBArIOUKs8RiRvei077uwpR66V1l_LtujNPj4VR3ZxhzkAnAK7T2pLdL37ysbVjpyoXMlt0AzTpoykj7osAtPPoFn5u1r9s5tOISWPuvqkXH_yGisBBckqRTZ73KfBOCt_lXk4B1l5TuktJ9Uq0-73VoVV1Y_13zL_4BBhuOow</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2806657298</pqid></control><display><type>article</type><title>An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing</title><source>Springer Nature OA Free Journals</source><source>EZB-FREE-00999 freely available EZB journals</source><creator>Ginhac, Dominique ; Dubois, Jérôme ; Paindavoine, Michel ; Heyrman, Barthélémy</creator><creatorcontrib>Ginhac, Dominique ; Dubois, Jérôme ; Paindavoine, Michel ; Heyrman, Barthélémy</creatorcontrib><description>A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators are implemented on the circuit. Each pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A
pixel proof-of-concept chip was fabricated in a 0.35
m standard CMOS process, with a pixel size of 35
m
35
m. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. The chip can capture raw images up to 10 000 frames per second and runs low-level image processing at a framerate of 2 000 to 5 000 frames per second.</description><identifier>ISSN: 1687-3963</identifier><identifier>ISSN: 1687-3955</identifier><identifier>EISSN: 1687-3963</identifier><identifier>DOI: 10.1155/2008/961315</identifier><language>eng</language><publisher>Cham: Springer International Publishing</publisher><subject>Arithmetic and logic units ; Array processors ; Circuits and Systems ; Computer Science ; Control Structures and Microprogramming ; Cost reduction ; Design ; Design and Architectures for Signal and Image Processing 2008 ; Digital cameras ; Electronic Circuits and Devices ; Engineering ; Engineering Sciences ; Focal plane ; Frames (data processing) ; Frames per second ; High speed ; Image acquisition ; Image and Speech Processing ; Image processing ; Integrated circuits ; Microprocessors ; Noise ; Photodiodes ; Pixels ; Processing speed ; Research Article ; Sensors ; Signal ; Signal and Image processing ; Vision systems</subject><ispartof>EURASIP journal on embedded systems, 2009-01, Vol.2008 (1), p.961315, Article 961315</ispartof><rights>Dominique Ginhac et al. 2008. This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.</rights><rights>Dominique Ginhac et al. 2008. This article is published under license to BioMed Central Ltd. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. This work is published under http://creativecommons.org/licenses/by/2.0/ (the “License”). Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License.</rights><rights>Copyright © 2008 Dominique Ginhac et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.</rights><rights>Distributed under a Creative Commons Attribution 4.0 International License</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c427t-bf1e723341eb33c2ef3b50970d8fc8971a44a17f5b6bb423d362e61b58049e043</citedby><cites>FETCH-LOGICAL-c427t-bf1e723341eb33c2ef3b50970d8fc8971a44a17f5b6bb423d362e61b58049e043</cites><orcidid>0000-0002-5911-2010 ; 0000-0003-1642-8311</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1155/2008/961315$$EPDF$$P50$$Gspringer$$Hfree_for_read</linktopdf><linktohtml>$$Uhttps://doi.org/10.1155/2008/961315$$EHTML$$P50$$Gspringer$$Hfree_for_read</linktohtml><link.rule.ids>230,314,777,781,882,27905,27906,41101,42170,51557</link.rule.ids><backlink>$$Uhttps://hal.science/hal-00517911$$DView record in HAL$$Hfree_for_read</backlink></links><search><creatorcontrib>Ginhac, Dominique</creatorcontrib><creatorcontrib>Dubois, Jérôme</creatorcontrib><creatorcontrib>Paindavoine, Michel</creatorcontrib><creatorcontrib>Heyrman, Barthélémy</creatorcontrib><title>An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing</title><title>EURASIP journal on embedded systems</title><addtitle>J Embedded Systems</addtitle><description>A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators are implemented on the circuit. Each pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A
pixel proof-of-concept chip was fabricated in a 0.35
m standard CMOS process, with a pixel size of 35
m
35
m. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. The chip can capture raw images up to 10 000 frames per second and runs low-level image processing at a framerate of 2 000 to 5 000 frames per second.</description><subject>Arithmetic and logic units</subject><subject>Array processors</subject><subject>Circuits and Systems</subject><subject>Computer Science</subject><subject>Control Structures and Microprogramming</subject><subject>Cost reduction</subject><subject>Design</subject><subject>Design and Architectures for Signal and Image Processing 2008</subject><subject>Digital cameras</subject><subject>Electronic Circuits and Devices</subject><subject>Engineering</subject><subject>Engineering Sciences</subject><subject>Focal plane</subject><subject>Frames (data processing)</subject><subject>Frames per second</subject><subject>High speed</subject><subject>Image acquisition</subject><subject>Image and Speech Processing</subject><subject>Image processing</subject><subject>Integrated circuits</subject><subject>Microprocessors</subject><subject>Noise</subject><subject>Photodiodes</subject><subject>Pixels</subject><subject>Processing speed</subject><subject>Research Article</subject><subject>Sensors</subject><subject>Signal</subject><subject>Signal and Image processing</subject><subject>Vision systems</subject><issn>1687-3963</issn><issn>1687-3955</issn><issn>1687-3963</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2009</creationdate><recordtype>article</recordtype><sourceid>C6C</sourceid><sourceid>ABUWG</sourceid><sourceid>AFKRA</sourceid><sourceid>AZQEC</sourceid><sourceid>BENPR</sourceid><sourceid>CCPQU</sourceid><sourceid>DWQXO</sourceid><sourceid>GNUQQ</sourceid><recordid>eNp10VtLwzAUB_AiCl6f_AJBQRCty8m9j2NeNpg48PIa0i7tIr3MZFP89rZUVESfEsIvJ-fkH0WHgC8AOB8QjNUgEUCBb0Q7IJSMaSLo5o_9drQbwjPGTCiqdqLbYY3uJ7eXaOabwpuqMmlp0ZMLrqnRaOGW6M2tFmjsikV8v7R2jq6bzJRoVpraokllCttdzWwIri72o63clMEefK570eP11cNoHE_vbiaj4TTOGJGrOM3BSkIpA5tSmhGb05TjROK5yjOVSDCMGZA5T0WaMkLnVBArIOUKs8RiRvei077uwpR66V1l_LtujNPj4VR3ZxhzkAnAK7T2pLdL37ysbVjpyoXMlt0AzTpoykj7osAtPPoFn5u1r9s5tOISWPuvqkXH_yGisBBckqRTZ73KfBOCt_lXk4B1l5TuktJ9Uq0-73VoVV1Y_13zL_4BBhuOow</recordid><startdate>20090118</startdate><enddate>20090118</enddate><creator>Ginhac, Dominique</creator><creator>Dubois, Jérôme</creator><creator>Paindavoine, Michel</creator><creator>Heyrman, Barthélémy</creator><general>Springer International Publishing</general><general>Springer Nature B.V</general><general>SpringerOpen</general><scope>C6C</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>3V.</scope><scope>7SC</scope><scope>7XB</scope><scope>8AL</scope><scope>8FD</scope><scope>8FE</scope><scope>8FG</scope><scope>8FK</scope><scope>ABUWG</scope><scope>AFKRA</scope><scope>ARAPS</scope><scope>AZQEC</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>DWQXO</scope><scope>GNUQQ</scope><scope>HCIFZ</scope><scope>JQ2</scope><scope>K7-</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>M0N</scope><scope>P5Z</scope><scope>P62</scope><scope>PIMPY</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>PRINS</scope><scope>Q9U</scope><scope>1XC</scope><scope>VOOES</scope><orcidid>https://orcid.org/0000-0002-5911-2010</orcidid><orcidid>https://orcid.org/0000-0003-1642-8311</orcidid></search><sort><creationdate>20090118</creationdate><title>An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing</title><author>Ginhac, Dominique ; Dubois, Jérôme ; Paindavoine, Michel ; Heyrman, Barthélémy</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c427t-bf1e723341eb33c2ef3b50970d8fc8971a44a17f5b6bb423d362e61b58049e043</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Arithmetic and logic units</topic><topic>Array processors</topic><topic>Circuits and Systems</topic><topic>Computer Science</topic><topic>Control Structures and Microprogramming</topic><topic>Cost reduction</topic><topic>Design</topic><topic>Design and Architectures for Signal and Image Processing 2008</topic><topic>Digital cameras</topic><topic>Electronic Circuits and Devices</topic><topic>Engineering</topic><topic>Engineering Sciences</topic><topic>Focal plane</topic><topic>Frames (data processing)</topic><topic>Frames per second</topic><topic>High speed</topic><topic>Image acquisition</topic><topic>Image and Speech Processing</topic><topic>Image processing</topic><topic>Integrated circuits</topic><topic>Microprocessors</topic><topic>Noise</topic><topic>Photodiodes</topic><topic>Pixels</topic><topic>Processing speed</topic><topic>Research Article</topic><topic>Sensors</topic><topic>Signal</topic><topic>Signal and Image processing</topic><topic>Vision systems</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Ginhac, Dominique</creatorcontrib><creatorcontrib>Dubois, Jérôme</creatorcontrib><creatorcontrib>Paindavoine, Michel</creatorcontrib><creatorcontrib>Heyrman, Barthélémy</creatorcontrib><collection>Springer Nature OA Free Journals</collection><collection>CrossRef</collection><collection>ProQuest Central (Corporate)</collection><collection>Computer and Information Systems Abstracts</collection><collection>ProQuest Central (purchase pre-March 2016)</collection><collection>Computing Database (Alumni Edition)</collection><collection>Technology Research Database</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>ProQuest Central (Alumni) (purchase pre-March 2016)</collection><collection>ProQuest Central (Alumni Edition)</collection><collection>ProQuest Central UK/Ireland</collection><collection>Advanced Technologies & Aerospace Collection</collection><collection>ProQuest Central Essentials</collection><collection>ProQuest Central</collection><collection>Technology Collection</collection><collection>ProQuest One Community College</collection><collection>ProQuest Central Korea</collection><collection>ProQuest Central Student</collection><collection>SciTech Premium Collection</collection><collection>ProQuest Computer Science Collection</collection><collection>Computer Science Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Computing Database</collection><collection>Advanced Technologies & Aerospace Database</collection><collection>ProQuest Advanced Technologies & Aerospace Collection</collection><collection>Publicly Available Content Database</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>ProQuest Central China</collection><collection>ProQuest Central Basic</collection><collection>Hyper Article en Ligne (HAL)</collection><collection>Hyper Article en Ligne (HAL) (Open Access)</collection><jtitle>EURASIP journal on embedded systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Ginhac, Dominique</au><au>Dubois, Jérôme</au><au>Paindavoine, Michel</au><au>Heyrman, Barthélémy</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing</atitle><jtitle>EURASIP journal on embedded systems</jtitle><stitle>J Embedded Systems</stitle><date>2009-01-18</date><risdate>2009</risdate><volume>2008</volume><issue>1</issue><spage>961315</spage><pages>961315-</pages><artnum>961315</artnum><issn>1687-3963</issn><issn>1687-3955</issn><eissn>1687-3963</eissn><abstract>A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators are implemented on the circuit. Each pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A
pixel proof-of-concept chip was fabricated in a 0.35
m standard CMOS process, with a pixel size of 35
m
35
m. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. The chip can capture raw images up to 10 000 frames per second and runs low-level image processing at a framerate of 2 000 to 5 000 frames per second.</abstract><cop>Cham</cop><pub>Springer International Publishing</pub><doi>10.1155/2008/961315</doi><orcidid>https://orcid.org/0000-0002-5911-2010</orcidid><orcidid>https://orcid.org/0000-0003-1642-8311</orcidid><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 1687-3963 |
| ispartof | EURASIP journal on embedded systems, 2009-01, Vol.2008 (1), p.961315, Article 961315 |
| issn | 1687-3963 1687-3955 1687-3963 |
| language | eng |
| recordid | cdi_hal_primary_oai_HAL_hal_00517911v1 |
| source | Springer Nature OA Free Journals; EZB-FREE-00999 freely available EZB journals |
| subjects | Arithmetic and logic units Array processors Circuits and Systems Computer Science Control Structures and Microprogramming Cost reduction Design Design and Architectures for Signal and Image Processing 2008 Digital cameras Electronic Circuits and Devices Engineering Engineering Sciences Focal plane Frames (data processing) Frames per second High speed Image acquisition Image and Speech Processing Image processing Integrated circuits Microprocessors Noise Photodiodes Pixels Processing speed Research Article Sensors Signal Signal and Image processing Vision systems |
| title | An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-20T18%3A41%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_hal_p&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=An%20SIMD%20Programmable%20Vision%20Chip%20with%20High-Speed%20Focal%20Plane%20Image%20Processing&rft.jtitle=EURASIP%20journal%20on%20embedded%20systems&rft.au=Ginhac,%20Dominique&rft.date=2009-01-18&rft.volume=2008&rft.issue=1&rft.spage=961315&rft.pages=961315-&rft.artnum=961315&rft.issn=1687-3963&rft.eissn=1687-3963&rft_id=info:doi/10.1155/2008/961315&rft_dat=%3Cproquest_hal_p%3E2806657298%3C/proquest_hal_p%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2806657298&rft_id=info:pmid/&rfr_iscdi=true |