Distributed synthesis for well-connected architectures

We study the synthesis problem for external linear or branching specifications and distributed, synchronous architectures with arbitrary delays on processes. External means that the specification only relates input and output variables. We introduce the subclass of uniformly well-connected (UWC) arc...

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Veröffentlicht in:	Formal methods in system design 2009-06, Vol.34 (3), p.215-237
Hauptverfasser:	Gastin, Paul, Sznajder, Nathalie, Zeitoun, Marc
Format:	Artikel
Sprache:	eng
Schlagworte:	Architecture CAE) and Design Circuits and Systems Computer Science Computer Science and Game Theory Computer-Aided Engineering (CAD Constrictions Delay Distributed, Parallel, and Cluster Computing Electrical Engineering Engineering Formal method Software Engineering/Programming and Operating Systems Specifications Synchronous Synthesis Systems design
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