Optimal Detector Design for On-line Testing of Linear Analog Systems

Optimal Detector Design for On-line Testing of Linear Analog Systems

The design of integrated fault detector for on-line testing of linear analog systems is discussed in this paper. The method consists in a concurrent processing of available the node voltage signals to provide a residual on-line, that carries information about the faults. Contrary to the few previous...

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Veröffentlicht in:VLSI Design 2000-01, Vol.2000 (1), p.59-74
1. Verfasser: Simeu, Emmanuel
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description The design of integrated fault detector for on-line testing of linear analog systems is discussed in this paper. The method consists in a concurrent processing of available the node voltage signals to provide a residual on-line, that carries information about the faults. Contrary to the few previous works dealing with the particular case of state variable analog systems, the method proposed here is useable without limitation for a larger class of linear analog systems, even when the state variables are not available as measurable voltages. For this purpose, an algorithm providing an extended state space model for any linear analog system from its netlist description is developed and implemented.
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Microelectronics
title Optimal Detector Design for On-line Testing of Linear Analog Systems
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