High-Performance LiNbO[sub.3] Domain Wall Memory Devices with Enhanced Selectivity via Optimized Metal–Semiconductor Contact

Lithium niobate (LiNbO[sub.3] ) single-crystal nanodevices featuring elevated readout domain wall currents exhibit significant potential for integrated circuits in memory computing applications. Nevertheless, challenges stem from suboptimal electrode–LiNbO[sub.3] single crystal contact characteristics, which impact the stability of high currents within these devices. In this work, we concentrate on augmenting the domain wall current by refining the fabrication processes of domain wall random access memory (DWRAM). Each LiNbO[sub.3] domain wall nanodevice was fabricated using a self-aligned process. Device performance was significantly enhanced by introducing a 10 nm interlayer between the LiNbO[sub.3] and Cu electrodes. A comparative analysis of electrical properties was conducted on devices with interlayers made of chromium (Cr) and titanium (Ti), as well as devices without interlayers. After the introduction of the Ti interlayer, the device’s coercive voltage demonstrated an 82% reduction, while the current density showed a remarkable 94-fold increase. A 100 nm sized device with the Ti interlayer underwent positive down–negative up pulse testing, demonstrating a writing time of 82 ns at 8 V and an erasing time of 12 μs at −9 V. These operating speeds are significantly faster than those of devices without interlayers. Moreover, the enhanced devices exhibited symmetrical domain switching hysteresis loops with retention times exceeding 10[sup.6] s. Notably, the coercive voltage (V [sub.c] ) dispersion remained narrow after more than 1000 switching cycles. At an elevated temperature of 400 K, the device’s on/off ratio was maintained at 10[sup.5] . The device’s embedded selector demonstrated an ultrahigh selectivity (>10[sup.6] ) across various reading voltages. These results underscore the viability of high-density nanoscale integration of ferroelectric domain wall memory.