CONTROL MEMORY ORGANIZATION

In a microprogrammed data processing system wherein the execution of a microinstruction sequence may be interrupted at any time for the execution of a more prioritary microinstruction sequence, the control memory is organized in such a way as to provide microinstructions of variable length. The basic length of the microinstructions is defined by the parallelism of a first control memory (1). With regard to a first range of addresses of the first control memory, a second control memory (17), read in parallel to the first one, provides a microinstruction field which is added to the basic field of the first memory and increases the microinstruction length. With regard to the remaining field of addresses of the first control memory, a first microinstruction may load with one of its bit fields a register (22). Then such bit field is associated to the subsequent microinstruction for increasing the length of it. In this case, in order to avoid that the execution of such longer subsequent microinstruction be affected by a microprogram interruption occurring within the execution of the first microinstruction and the reading out of the subsequent one, some logic circuits (25, 26, 27, 28, 29, 30) defers, in case of interruption, the association of the bit field to the subsequent microinstruction till the return to the interrupted microprogram.