METHOD FOR TESTING AND FOR GENERATING A MAPPING FOR AN ELECTRONIC DEVICE

In a method for generating a mapping of logical addresses to a layout of an electronic circuit structure first and second relations are established. The first relation is representative of the mapping of signal pairs to the layout and the second relation is representative of the mapping of the logic...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	BRACHA, GABRIEL, WEISBERGER, EYTAN
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING
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