METHOD FOR TESTING AND FOR GENERATING A MAPPING FOR AN ELECTRONIC DEVICE
In a method for generating a mapping of logical addresses to a layout of an electronic circuit structure first and second relations are established. The first relation is representative of the mapping of signal pairs to the layout and the second relation is representative of the mapping of the logic...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | eng ; fre |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | BRACHA, GABRIEL WEISBERGER, EYTAN |
| description | In a method for generating a mapping of logical addresses to a layout of an electronic circuit structure first and second relations are established. The first relation is representative of the mapping of signal pairs to the layout and the second relation is representative of the mapping of the logical addresses to the signal pairs. Joining of the first and second relations yields a mapping table which can be used for purposes of circuit testing and design.
Dans un procédé destiné à produire une topographie d'adresses logiques correspondant à un schéma d'une structure de circuit électronique, on établit une première et une deuxième relation. La première relation représente une topographie de paires de signaux correspondant au schéma, et la deuxième relation représente une topographie d'adresses logiques correspondant aux paires de signaux. L'assemblage de la première et de la deuxième relation permet d'obtenir un tableau topographique pouvant être utilisé à des fins de test et de mise au point de circuits. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_WO9816881A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>WO9816881A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_WO9816881A13</originalsourceid><addsrcrecordid>eNrjZPDwdQ3x8HdRcPMPUghxDQ7x9HNXcPSD8N1d_VyDHCFCCr6OAQEgFkjC0U_B1cfVOSTI38_TWcHFNczT2ZWHgTUtMac4lRdKczMouLmGOHvophbkx6cWFyQmp-allsSH-1taGJpZWBg6GhoToQQAd6gsKg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD FOR TESTING AND FOR GENERATING A MAPPING FOR AN ELECTRONIC DEVICE</title><source>esp@cenet</source><creator>BRACHA, GABRIEL ; WEISBERGER, EYTAN</creator><creatorcontrib>BRACHA, GABRIEL ; WEISBERGER, EYTAN</creatorcontrib><description>In a method for generating a mapping of logical addresses to a layout of an electronic circuit structure first and second relations are established. The first relation is representative of the mapping of signal pairs to the layout and the second relation is representative of the mapping of the logical addresses to the signal pairs. Joining of the first and second relations yields a mapping table which can be used for purposes of circuit testing and design.
Dans un procédé destiné à produire une topographie d'adresses logiques correspondant à un schéma d'une structure de circuit électronique, on établit une première et une deuxième relation. La première relation représente une topographie de paires de signaux correspondant au schéma, et la deuxième relation représente une topographie d'adresses logiques correspondant aux paires de signaux. L'assemblage de la première et de la deuxième relation permet d'obtenir un tableau topographique pouvant être utilisé à des fins de test et de mise au point de circuits.</description><edition>6</edition><language>eng ; fre</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; SEMICONDUCTOR DEVICES ; TESTING</subject><creationdate>1998</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19980423&DB=EPODOC&CC=WO&NR=9816881A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19980423&DB=EPODOC&CC=WO&NR=9816881A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BRACHA, GABRIEL</creatorcontrib><creatorcontrib>WEISBERGER, EYTAN</creatorcontrib><title>METHOD FOR TESTING AND FOR GENERATING A MAPPING FOR AN ELECTRONIC DEVICE</title><description>In a method for generating a mapping of logical addresses to a layout of an electronic circuit structure first and second relations are established. The first relation is representative of the mapping of signal pairs to the layout and the second relation is representative of the mapping of the logical addresses to the signal pairs. Joining of the first and second relations yields a mapping table which can be used for purposes of circuit testing and design.
Dans un procédé destiné à produire une topographie d'adresses logiques correspondant à un schéma d'une structure de circuit électronique, on établit une première et une deuxième relation. La première relation représente une topographie de paires de signaux correspondant au schéma, et la deuxième relation représente une topographie d'adresses logiques correspondant aux paires de signaux. L'assemblage de la première et de la deuxième relation permet d'obtenir un tableau topographique pouvant être utilisé à des fins de test et de mise au point de circuits.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1998</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPDwdQ3x8HdRcPMPUghxDQ7x9HNXcPSD8N1d_VyDHCFCCr6OAQEgFkjC0U_B1cfVOSTI38_TWcHFNczT2ZWHgTUtMac4lRdKczMouLmGOHvophbkx6cWFyQmp-allsSH-1taGJpZWBg6GhoToQQAd6gsKg</recordid><startdate>19980423</startdate><enddate>19980423</enddate><creator>BRACHA, GABRIEL</creator><creator>WEISBERGER, EYTAN</creator><scope>EVB</scope></search><sort><creationdate>19980423</creationdate><title>METHOD FOR TESTING AND FOR GENERATING A MAPPING FOR AN ELECTRONIC DEVICE</title><author>BRACHA, GABRIEL ; WEISBERGER, EYTAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO9816881A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>1998</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>BRACHA, GABRIEL</creatorcontrib><creatorcontrib>WEISBERGER, EYTAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BRACHA, GABRIEL</au><au>WEISBERGER, EYTAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR TESTING AND FOR GENERATING A MAPPING FOR AN ELECTRONIC DEVICE</title><date>1998-04-23</date><risdate>1998</risdate><abstract>In a method for generating a mapping of logical addresses to a layout of an electronic circuit structure first and second relations are established. The first relation is representative of the mapping of signal pairs to the layout and the second relation is representative of the mapping of the logical addresses to the signal pairs. Joining of the first and second relations yields a mapping table which can be used for purposes of circuit testing and design.
Dans un procédé destiné à produire une topographie d'adresses logiques correspondant à un schéma d'une structure de circuit électronique, on établit une première et une deuxième relation. La première relation représente une topographie de paires de signaux correspondant au schéma, et la deuxième relation représente une topographie d'adresses logiques correspondant aux paires de signaux. L'assemblage de la première et de la deuxième relation permet d'obtenir un tableau topographique pouvant être utilisé à des fins de test et de mise au point de circuits.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; fre |
| recordid | cdi_epo_espacenet_WO9816881A1 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING |
| title | METHOD FOR TESTING AND FOR GENERATING A MAPPING FOR AN ELECTRONIC DEVICE |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T04%3A29%3A38IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BRACHA,%20GABRIEL&rft.date=1998-04-23&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EWO9816881A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |