METHOD AND APPARATUS FOR DEMODULATING A RECEIVED SIGNAL
A demodulator (18) which receives digital representations of a received signal converts those signals into analog signals (53) in a pair of multiplying analog-to-digital converters (MDACs) (21, 22). The analog signals are then combined in combiner (26) by subtracting the first analog signal from the...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng ; fre |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | TRAYLOR, KEVIN, BRUCE |
| description | A demodulator (18) which receives digital representations of a received signal converts those signals into analog signals (53) in a pair of multiplying analog-to-digital converters (MDACs) (21, 22). The analog signals are then combined in combiner (26) by subtracting the first analog signal from the second analog signal (54). The summed signal is normalized (55) in quantizer (27). The output from the quantizer (27) is accumulated (56) in an n-bit accumulator (28) as regulated by a clock input (Fclock). The output of the accumulator (28) is used as a programming input (57) to the MDACs (21, 22).
Un démodulateur (18), lequel reçoit des représentations numériques d'un signal reçu, convertit ces signaux en signaux analogiques (53) dans une paire de numériseurs multiplieurs (MDAC) (21, 22). Les signaux analogiques sont ensuite combinés dans un combineur (26) par soustraction du premier signal analogique du second signal analogique (54). Le signal ajouté est normalisé (55) dans un quantificateur (27). La sortie du quantificateur (27) est accumulée (56) dans un accumulateur n-bits (28) régulé par une entrée d'horloge (Fhorloge). La sortie de l'accumulateur (28) est utilisée comme entrée de programmation (57) dans les MDAC (21, 22). |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_WO9723981A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>WO9723981A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_WO9723981A13</originalsourceid><addsrcrecordid>eNrjZDD3dQ3x8HdRcPQD4oAAxyDHkNBgBTf_IAUXV19_l1AfxxBPP3cFR4UgV2dXzzBXF4VgT3c_Rx8eBta0xJziVF4ozc2g4OYa4uyhm1qQH59aXJCYnJqXWhIf7m9pbmRsaWHoaGhMhBIA2OUnxQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD AND APPARATUS FOR DEMODULATING A RECEIVED SIGNAL</title><source>esp@cenet</source><creator>TRAYLOR, KEVIN, BRUCE</creator><creatorcontrib>TRAYLOR, KEVIN, BRUCE</creatorcontrib><description>A demodulator (18) which receives digital representations of a received signal converts those signals into analog signals (53) in a pair of multiplying analog-to-digital converters (MDACs) (21, 22). The analog signals are then combined in combiner (26) by subtracting the first analog signal from the second analog signal (54). The summed signal is normalized (55) in quantizer (27). The output from the quantizer (27) is accumulated (56) in an n-bit accumulator (28) as regulated by a clock input (Fclock). The output of the accumulator (28) is used as a programming input (57) to the MDACs (21, 22).
Un démodulateur (18), lequel reçoit des représentations numériques d'un signal reçu, convertit ces signaux en signaux analogiques (53) dans une paire de numériseurs multiplieurs (MDAC) (21, 22). Les signaux analogiques sont ensuite combinés dans un combineur (26) par soustraction du premier signal analogique du second signal analogique (54). Le signal ajouté est normalisé (55) dans un quantificateur (27). La sortie du quantificateur (27) est accumulée (56) dans un accumulateur n-bits (28) régulé par une entrée d'horloge (Fhorloge). La sortie de l'accumulateur (28) est utilisée comme entrée de programmation (57) dans les MDAC (21, 22).</description><edition>6</edition><language>eng ; fre</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>1997</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19970703&DB=EPODOC&CC=WO&NR=9723981A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19970703&DB=EPODOC&CC=WO&NR=9723981A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TRAYLOR, KEVIN, BRUCE</creatorcontrib><title>METHOD AND APPARATUS FOR DEMODULATING A RECEIVED SIGNAL</title><description>A demodulator (18) which receives digital representations of a received signal converts those signals into analog signals (53) in a pair of multiplying analog-to-digital converters (MDACs) (21, 22). The analog signals are then combined in combiner (26) by subtracting the first analog signal from the second analog signal (54). The summed signal is normalized (55) in quantizer (27). The output from the quantizer (27) is accumulated (56) in an n-bit accumulator (28) as regulated by a clock input (Fclock). The output of the accumulator (28) is used as a programming input (57) to the MDACs (21, 22).
Un démodulateur (18), lequel reçoit des représentations numériques d'un signal reçu, convertit ces signaux en signaux analogiques (53) dans une paire de numériseurs multiplieurs (MDAC) (21, 22). Les signaux analogiques sont ensuite combinés dans un combineur (26) par soustraction du premier signal analogique du second signal analogique (54). Le signal ajouté est normalisé (55) dans un quantificateur (27). La sortie du quantificateur (27) est accumulée (56) dans un accumulateur n-bits (28) régulé par une entrée d'horloge (Fhorloge). La sortie de l'accumulateur (28) est utilisée comme entrée de programmation (57) dans les MDAC (21, 22).</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1997</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD3dQ3x8HdRcPQD4oAAxyDHkNBgBTf_IAUXV19_l1AfxxBPP3cFR4UgV2dXzzBXF4VgT3c_Rx8eBta0xJziVF4ozc2g4OYa4uyhm1qQH59aXJCYnJqXWhIf7m9pbmRsaWHoaGhMhBIA2OUnxQ</recordid><startdate>19970703</startdate><enddate>19970703</enddate><creator>TRAYLOR, KEVIN, BRUCE</creator><scope>EVB</scope></search><sort><creationdate>19970703</creationdate><title>METHOD AND APPARATUS FOR DEMODULATING A RECEIVED SIGNAL</title><author>TRAYLOR, KEVIN, BRUCE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO9723981A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>1997</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>TRAYLOR, KEVIN, BRUCE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TRAYLOR, KEVIN, BRUCE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD AND APPARATUS FOR DEMODULATING A RECEIVED SIGNAL</title><date>1997-07-03</date><risdate>1997</risdate><abstract>A demodulator (18) which receives digital representations of a received signal converts those signals into analog signals (53) in a pair of multiplying analog-to-digital converters (MDACs) (21, 22). The analog signals are then combined in combiner (26) by subtracting the first analog signal from the second analog signal (54). The summed signal is normalized (55) in quantizer (27). The output from the quantizer (27) is accumulated (56) in an n-bit accumulator (28) as regulated by a clock input (Fclock). The output of the accumulator (28) is used as a programming input (57) to the MDACs (21, 22).
Un démodulateur (18), lequel reçoit des représentations numériques d'un signal reçu, convertit ces signaux en signaux analogiques (53) dans une paire de numériseurs multiplieurs (MDAC) (21, 22). Les signaux analogiques sont ensuite combinés dans un combineur (26) par soustraction du premier signal analogique du second signal analogique (54). Le signal ajouté est normalisé (55) dans un quantificateur (27). La sortie du quantificateur (27) est accumulée (56) dans un accumulateur n-bits (28) régulé par une entrée d'horloge (Fhorloge). La sortie de l'accumulateur (28) est utilisée comme entrée de programmation (57) dans les MDAC (21, 22).</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; fre |
| recordid | cdi_epo_espacenet_WO9723981A1 |
| source | esp@cenet |
| subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
| title | METHOD AND APPARATUS FOR DEMODULATING A RECEIVED SIGNAL |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T14%3A19%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=TRAYLOR,%20KEVIN,%20BRUCE&rft.date=1997-07-03&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EWO9723981A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |