SINGLE-STACK IMPLEMENTATION OF A REED-SOLOMON ENCODER/DECODER

An error correction unit (20, 22, 24) using a single stack architecture (24, 40, 42, 44) plus evaluation logic (46) for generating, reducing and evaluating polynomials involved in correction with a Reed-Solomon code is disclosed. The same hardware is sequentially used to generate the syndromes, and...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	OWSLEY, PATRICK, A, FRENCH, CATHERINE, A, BERGE, TORKJELL
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING CODE CONVERSION IN GENERAL CODING COMPUTING COUNTING DECODING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS
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