TRIGGER UNIT DESIGN METHOD
A trigger unit design method. The design method comprises: in a digital circuit, analyzing a signal delay of a clock control signal; according to the signal delay of the clock control signal, selecting a clock gating circuit from a plurality of different types of clock gating circuits; combining at...
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| creator | CHEN, Xiangdong SONG, Weiquan |
| description | A trigger unit design method. The design method comprises: in a digital circuit, analyzing a signal delay of a clock control signal; according to the signal delay of the clock control signal, selecting a clock gating circuit from a plurality of different types of clock gating circuits; combining at least one edge trigger with the selected clock gating circuit to form a trigger unit, wherein the plurality of different types of clock gating circuits enable or shield the first clock signal according to the clock control signal so as to generate a second clock signal, and the edge trigger transmits data at the edge of the second clock signal. In the trigger unit design method, a clock gating circuit is selected from a plurality of different types of clock gating circuits according to a delay condition of a clock control signal, which not only allows for eliminating glitches from clock signals generated by the clock gating circuit, but also reduces the number of logic elements of the clock gating circuit and decre |
| format | Patent |
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The design method comprises: in a digital circuit, analyzing a signal delay of a clock control signal; according to the signal delay of the clock control signal, selecting a clock gating circuit from a plurality of different types of clock gating circuits; combining at least one edge trigger with the selected clock gating circuit to form a trigger unit, wherein the plurality of different types of clock gating circuits enable or shield the first clock signal according to the clock control signal so as to generate a second clock signal, and the edge trigger transmits data at the edge of the second clock signal. In the trigger unit design method, a clock gating circuit is selected from a plurality of different types of clock gating circuits according to a delay condition of a clock control signal, which not only allows for eliminating glitches from clock signals generated by the clock gating circuit, but also reduces the number of logic elements of the clock gating circuit and decre</description><language>chi ; eng ; fre</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230803&DB=EPODOC&CC=WO&NR=2023143631A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25551,76302</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230803&DB=EPODOC&CC=WO&NR=2023143631A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHEN, Xiangdong</creatorcontrib><creatorcontrib>SONG, Weiquan</creatorcontrib><title>TRIGGER UNIT DESIGN METHOD</title><description>A trigger unit design method. The design method comprises: in a digital circuit, analyzing a signal delay of a clock control signal; according to the signal delay of the clock control signal, selecting a clock gating circuit from a plurality of different types of clock gating circuits; combining at least one edge trigger with the selected clock gating circuit to form a trigger unit, wherein the plurality of different types of clock gating circuits enable or shield the first clock signal according to the clock control signal so as to generate a second clock signal, and the edge trigger transmits data at the edge of the second clock signal. In the trigger unit design method, a clock gating circuit is selected from a plurality of different types of clock gating circuits according to a delay condition of a clock control signal, which not only allows for eliminating glitches from clock signals generated by the clock gating circuit, but also reduces the number of logic elements of the clock gating circuit and decre</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAKCfJ0d3cNUgj18wxRcHEN9nT3U_B1DfHwd-FhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfHh_kYGRsaGJsZmxoaOhsbEqQIArbYhEg</recordid><startdate>20230803</startdate><enddate>20230803</enddate><creator>CHEN, Xiangdong</creator><creator>SONG, Weiquan</creator><scope>EVB</scope></search><sort><creationdate>20230803</creationdate><title>TRIGGER UNIT DESIGN METHOD</title><author>CHEN, Xiangdong ; SONG, Weiquan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO2023143631A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng ; fre</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>CHEN, Xiangdong</creatorcontrib><creatorcontrib>SONG, Weiquan</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHEN, Xiangdong</au><au>SONG, Weiquan</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>TRIGGER UNIT DESIGN METHOD</title><date>2023-08-03</date><risdate>2023</risdate><abstract>A trigger unit design method. The design method comprises: in a digital circuit, analyzing a signal delay of a clock control signal; according to the signal delay of the clock control signal, selecting a clock gating circuit from a plurality of different types of clock gating circuits; combining at least one edge trigger with the selected clock gating circuit to form a trigger unit, wherein the plurality of different types of clock gating circuits enable or shield the first clock signal according to the clock control signal so as to generate a second clock signal, and the edge trigger transmits data at the edge of the second clock signal. In the trigger unit design method, a clock gating circuit is selected from a plurality of different types of clock gating circuits according to a delay condition of a clock control signal, which not only allows for eliminating glitches from clock signals generated by the clock gating circuit, but also reduces the number of logic elements of the clock gating circuit and decre</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng ; fre |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | TRIGGER UNIT DESIGN METHOD |
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