DRIVER CIRCUIT, DRIVING METHOD THEREFOR, ARRAY SUBSTRATE, AND DISPLAY APPARATUS
A driver circuit, comprising: a logic control module (CTR); and multiple pins (P) coupled to the logic control module (CTR). The multiple pins (P) comprise: a clock pin (CLKP), a data pin (DataP), and at least two output pins (OutP). The clock pin (CLKP) is configured to receive a clock signal (CLK)...
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| creator | GENG, Liguang CHA, Huangfei HAO, Wei SHANG, Xingce YIN, Kaimin ZHANG, Junwei DENG, Yu SU, Wengang WANG, Feifei DUAN, Taotao |
| description | A driver circuit, comprising: a logic control module (CTR); and multiple pins (P) coupled to the logic control module (CTR). The multiple pins (P) comprise: a clock pin (CLKP), a data pin (DataP), and at least two output pins (OutP). The clock pin (CLKP) is configured to receive a clock signal (CLK). The data pin (DataP) is configured to receive a data signal (Data) under the control of the logic control module (CTR) at a stage of a valid level of the clock signal (CLK). The logic control module (CTR) is configured to, according to the data signal (Data), generate a drive control signal corresponding to each output pin (OutP), so as to control an electrical signal via the output pin (OutP).
Un circuit d'attaque, celui-ci comprenant un module de commande logique (CTR) et de multiples broches (P) couplées au module de commande logique (CTR). Les multiples broches (P) comprennent une broche d'horloge (CLKP), une broche de données (DataP) et au moins deux broches de sortie (OutP). La broche d'horloge (CLKP) est c |
| format | Patent |
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Un circuit d'attaque, celui-ci comprenant un module de commande logique (CTR) et de multiples broches (P) couplées au module de commande logique (CTR). Les multiples broches (P) comprennent une broche d'horloge (CLKP), une broche de données (DataP) et au moins deux broches de sortie (OutP). La broche d'horloge (CLKP) est c</description><language>chi ; eng ; fre</language><subject>ADVERTISING ; ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION ; CRYPTOGRAPHY ; DISPLAY ; EDUCATION ; PHYSICS ; SEALS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230525&DB=EPODOC&CC=WO&NR=2023087155A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230525&DB=EPODOC&CC=WO&NR=2023087155A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GENG, Liguang</creatorcontrib><creatorcontrib>CHA, Huangfei</creatorcontrib><creatorcontrib>HAO, Wei</creatorcontrib><creatorcontrib>SHANG, Xingce</creatorcontrib><creatorcontrib>YIN, Kaimin</creatorcontrib><creatorcontrib>ZHANG, Junwei</creatorcontrib><creatorcontrib>DENG, Yu</creatorcontrib><creatorcontrib>SU, Wengang</creatorcontrib><creatorcontrib>WANG, Feifei</creatorcontrib><creatorcontrib>DUAN, Taotao</creatorcontrib><title>DRIVER CIRCUIT, DRIVING METHOD THEREFOR, ARRAY SUBSTRATE, AND DISPLAY APPARATUS</title><description>A driver circuit, comprising: a logic control module (CTR); and multiple pins (P) coupled to the logic control module (CTR). The multiple pins (P) comprise: a clock pin (CLKP), a data pin (DataP), and at least two output pins (OutP). The clock pin (CLKP) is configured to receive a clock signal (CLK). The data pin (DataP) is configured to receive a data signal (Data) under the control of the logic control module (CTR) at a stage of a valid level of the clock signal (CLK). The logic control module (CTR) is configured to, according to the data signal (Data), generate a drive control signal corresponding to each output pin (OutP), so as to control an electrical signal via the output pin (OutP).
Un circuit d'attaque, celui-ci comprenant un module de commande logique (CTR) et de multiples broches (P) couplées au module de commande logique (CTR). Les multiples broches (P) comprennent une broche d'horloge (CLKP), une broche de données (DataP) et au moins deux broches de sortie (OutP). La broche d'horloge (CLKP) est c</description><subject>ADVERTISING</subject><subject>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</subject><subject>CRYPTOGRAPHY</subject><subject>DISPLAY</subject><subject>EDUCATION</subject><subject>PHYSICS</subject><subject>SEALS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPB3CfIMcw1ScPYMcg71DNFRAPE9_dwVfF1DPPxdFEI8XINc3fyDdBQcg4IcIxWCQ52CQ4IcQ1yBAn4uCi6ewQE-QGHHgABHoGhoMA8Da1piTnEqL5TmZlB2cw1x9tBNLciPTy0uSExOzUstiQ_3NzIwMjawMDc0NXU0NCZOFQD9iS-0</recordid><startdate>20230525</startdate><enddate>20230525</enddate><creator>GENG, Liguang</creator><creator>CHA, Huangfei</creator><creator>HAO, Wei</creator><creator>SHANG, Xingce</creator><creator>YIN, Kaimin</creator><creator>ZHANG, Junwei</creator><creator>DENG, Yu</creator><creator>SU, Wengang</creator><creator>WANG, Feifei</creator><creator>DUAN, Taotao</creator><scope>EVB</scope></search><sort><creationdate>20230525</creationdate><title>DRIVER CIRCUIT, DRIVING METHOD THEREFOR, ARRAY SUBSTRATE, AND DISPLAY APPARATUS</title><author>GENG, Liguang ; CHA, Huangfei ; HAO, Wei ; SHANG, Xingce ; YIN, Kaimin ; ZHANG, Junwei ; DENG, Yu ; SU, Wengang ; WANG, Feifei ; DUAN, Taotao</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO2023087155A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng ; fre</language><creationdate>2023</creationdate><topic>ADVERTISING</topic><topic>ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION</topic><topic>CRYPTOGRAPHY</topic><topic>DISPLAY</topic><topic>EDUCATION</topic><topic>PHYSICS</topic><topic>SEALS</topic><toplevel>online_resources</toplevel><creatorcontrib>GENG, Liguang</creatorcontrib><creatorcontrib>CHA, Huangfei</creatorcontrib><creatorcontrib>HAO, Wei</creatorcontrib><creatorcontrib>SHANG, Xingce</creatorcontrib><creatorcontrib>YIN, Kaimin</creatorcontrib><creatorcontrib>ZHANG, Junwei</creatorcontrib><creatorcontrib>DENG, Yu</creatorcontrib><creatorcontrib>SU, Wengang</creatorcontrib><creatorcontrib>WANG, Feifei</creatorcontrib><creatorcontrib>DUAN, Taotao</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GENG, Liguang</au><au>CHA, Huangfei</au><au>HAO, Wei</au><au>SHANG, Xingce</au><au>YIN, Kaimin</au><au>ZHANG, Junwei</au><au>DENG, Yu</au><au>SU, Wengang</au><au>WANG, Feifei</au><au>DUAN, Taotao</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DRIVER CIRCUIT, DRIVING METHOD THEREFOR, ARRAY SUBSTRATE, AND DISPLAY APPARATUS</title><date>2023-05-25</date><risdate>2023</risdate><abstract>A driver circuit, comprising: a logic control module (CTR); and multiple pins (P) coupled to the logic control module (CTR). The multiple pins (P) comprise: a clock pin (CLKP), a data pin (DataP), and at least two output pins (OutP). The clock pin (CLKP) is configured to receive a clock signal (CLK). The data pin (DataP) is configured to receive a data signal (Data) under the control of the logic control module (CTR) at a stage of a valid level of the clock signal (CLK). The logic control module (CTR) is configured to, according to the data signal (Data), generate a drive control signal corresponding to each output pin (OutP), so as to control an electrical signal via the output pin (OutP).
Un circuit d'attaque, celui-ci comprenant un module de commande logique (CTR) et de multiples broches (P) couplées au module de commande logique (CTR). Les multiples broches (P) comprennent une broche d'horloge (CLKP), une broche de données (DataP) et au moins deux broches de sortie (OutP). La broche d'horloge (CLKP) est c</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION CRYPTOGRAPHY DISPLAY EDUCATION PHYSICS SEALS |
| title | DRIVER CIRCUIT, DRIVING METHOD THEREFOR, ARRAY SUBSTRATE, AND DISPLAY APPARATUS |
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