FLASH MEMORY CELL, AND MANUFACTURING METHOD, WRITING METHOD, AND ERASING METHOD THEREFOR

A flash memory cell (100) and a manufacturing method therefor, and a writing method and an erasing method for the flash memory cell (100). The flash memory cell (100) comprises: a substrate (101), comprising a deep well region (103) and a well region (102) provided on the deep well region (103); a f...

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Hauptverfasser: JIANG, Jiayong, SHI, Zhendong
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SHI, Zhendong
description A flash memory cell (100) and a manufacturing method therefor, and a writing method and an erasing method for the flash memory cell (100). The flash memory cell (100) comprises: a substrate (101), comprising a deep well region (103) and a well region (102) provided on the deep well region (103); a first storage transistor (110) and a second storage transistor (130) provided on the well region (102) and respectively storing first data and second data; and a gating transistor (120) provided between the first storage transistor (110) and the second storage transistor (130) on the well region (102) in a horizontal direction, and configured to isolate the first storage transistor (110) from the second storage transistor (130) and perform a gating operation on the first storage transistor (110) and the second storage transistor (130), wherein the first storage transistor (110), the gating transistor (120), and the second storage transistor (130) are sequentially connected in series, a source region of the first sto
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_WO2023025260A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>WO2023025260A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_WO2023025260A13</originalsourceid><addsrcrecordid>eNrjZIhw83EM9lDwdfX1D4pUcHb18dFRcPRzUfB19At1c3QOCQ3y9HMHSod4-LvoKIQHeYYg80EqXYMcgxFiCiEerkGubv5BPAysaYk5xam8UJqbQdnNNcTZQze1ID8-tbggMTk1L7UkPtzfyMDI2MDI1MjMwNHQmDhVAHlNMa8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>FLASH MEMORY CELL, AND MANUFACTURING METHOD, WRITING METHOD, AND ERASING METHOD THEREFOR</title><source>esp@cenet</source><creator>JIANG, Jiayong ; SHI, Zhendong</creator><creatorcontrib>JIANG, Jiayong ; SHI, Zhendong</creatorcontrib><description>A flash memory cell (100) and a manufacturing method therefor, and a writing method and an erasing method for the flash memory cell (100). The flash memory cell (100) comprises: a substrate (101), comprising a deep well region (103) and a well region (102) provided on the deep well region (103); a first storage transistor (110) and a second storage transistor (130) provided on the well region (102) and respectively storing first data and second data; and a gating transistor (120) provided between the first storage transistor (110) and the second storage transistor (130) on the well region (102) in a horizontal direction, and configured to isolate the first storage transistor (110) from the second storage transistor (130) and perform a gating operation on the first storage transistor (110) and the second storage transistor (130), wherein the first storage transistor (110), the gating transistor (120), and the second storage transistor (130) are sequentially connected in series, a source region of the first sto</description><language>chi ; eng ; fre</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230302&amp;DB=EPODOC&amp;CC=WO&amp;NR=2023025260A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230302&amp;DB=EPODOC&amp;CC=WO&amp;NR=2023025260A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JIANG, Jiayong</creatorcontrib><creatorcontrib>SHI, Zhendong</creatorcontrib><title>FLASH MEMORY CELL, AND MANUFACTURING METHOD, WRITING METHOD, AND ERASING METHOD THEREFOR</title><description>A flash memory cell (100) and a manufacturing method therefor, and a writing method and an erasing method for the flash memory cell (100). The flash memory cell (100) comprises: a substrate (101), comprising a deep well region (103) and a well region (102) provided on the deep well region (103); a first storage transistor (110) and a second storage transistor (130) provided on the well region (102) and respectively storing first data and second data; and a gating transistor (120) provided between the first storage transistor (110) and the second storage transistor (130) on the well region (102) in a horizontal direction, and configured to isolate the first storage transistor (110) from the second storage transistor (130) and perform a gating operation on the first storage transistor (110) and the second storage transistor (130), wherein the first storage transistor (110), the gating transistor (120), and the second storage transistor (130) are sequentially connected in series, a source region of the first sto</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZIhw83EM9lDwdfX1D4pUcHb18dFRcPRzUfB19At1c3QOCQ3y9HMHSod4-LvoKIQHeYYg80EqXYMcgxFiCiEerkGubv5BPAysaYk5xam8UJqbQdnNNcTZQze1ID8-tbggMTk1L7UkPtzfyMDI2MDI1MjMwNHQmDhVAHlNMa8</recordid><startdate>20230302</startdate><enddate>20230302</enddate><creator>JIANG, Jiayong</creator><creator>SHI, Zhendong</creator><scope>EVB</scope></search><sort><creationdate>20230302</creationdate><title>FLASH MEMORY CELL, AND MANUFACTURING METHOD, WRITING METHOD, AND ERASING METHOD THEREFOR</title><author>JIANG, Jiayong ; SHI, Zhendong</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO2023025260A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng ; fre</language><creationdate>2023</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>JIANG, Jiayong</creatorcontrib><creatorcontrib>SHI, Zhendong</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JIANG, Jiayong</au><au>SHI, Zhendong</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FLASH MEMORY CELL, AND MANUFACTURING METHOD, WRITING METHOD, AND ERASING METHOD THEREFOR</title><date>2023-03-02</date><risdate>2023</risdate><abstract>A flash memory cell (100) and a manufacturing method therefor, and a writing method and an erasing method for the flash memory cell (100). The flash memory cell (100) comprises: a substrate (101), comprising a deep well region (103) and a well region (102) provided on the deep well region (103); a first storage transistor (110) and a second storage transistor (130) provided on the well region (102) and respectively storing first data and second data; and a gating transistor (120) provided between the first storage transistor (110) and the second storage transistor (130) on the well region (102) in a horizontal direction, and configured to isolate the first storage transistor (110) from the second storage transistor (130) and perform a gating operation on the first storage transistor (110) and the second storage transistor (130), wherein the first storage transistor (110), the gating transistor (120), and the second storage transistor (130) are sequentially connected in series, a source region of the first sto</abstract><oa>free_for_read</oa></addata></record>
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subjects INFORMATION STORAGE
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STATIC STORES
title FLASH MEMORY CELL, AND MANUFACTURING METHOD, WRITING METHOD, AND ERASING METHOD THEREFOR
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T12%3A14%3A38IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=JIANG,%20Jiayong&rft.date=2023-03-02&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EWO2023025260A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true