COMPUTE-IN-MEMORY WITH TERNARY ACTIVATION

A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches respo...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	SRIVASTAVA, Ankit, MIRHAJ, Seyed Arash, WADHWA, Sameer, MOHAN, Suren, LI, Ren
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING INFORMATION STORAGE PHYSICS STATIC STORES
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