CHIP PACKAGE STRUCTURE AND ELECTRONIC DEVICE
Provided in the present disclosure are a chip package structure and an electronic device, which belong to the technical field of semiconductor chip package tests. The chip package structure comprises: a package substrate, the package substrate having a first surface and a second surface which are di...
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| creator | LAI, Yuanting SUN, Tuobei PANG, Jian |
| description | Provided in the present disclosure are a chip package structure and an electronic device, which belong to the technical field of semiconductor chip package tests. The chip package structure comprises: a package substrate, the package substrate having a first surface and a second surface which are disposed opposite each other; at least one chip, the chip being disposed inside the package substrate, and the chip having a third surface and a fourth surface disposed opposite each other, wherein the third surface is provided with a chip pin; and a heat dissipation structure, the heat dissipation structure being disposed inside the package substrate and located on the fourth surface of the chip, and the side surface of the heat dissipation structure away from the chip is exposed on the second surface of the package substrate, and the heat dissipation structure being used for providing a heat dissipation channel for the chip. FIG. 1
La présente invention concerne une structure d'encapsulation de puce et un dispositi |
| format | Patent |
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La présente invention concerne une structure d'encapsulation de puce et un dispositi</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNBx9vAMUAhwdPZ2dHdVCA4JCnUOCQ1yVXD0c1Fw9XF1Dgny9_N0VnBxDfN0duVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfHh_kYGRoZGxhamppaOhsbEqQIAGdUl-Q</recordid><startdate>20211202</startdate><enddate>20211202</enddate><creator>LAI, Yuanting</creator><creator>SUN, Tuobei</creator><creator>PANG, Jian</creator><scope>EVB</scope></search><sort><creationdate>20211202</creationdate><title>CHIP PACKAGE STRUCTURE AND ELECTRONIC DEVICE</title><author>LAI, Yuanting ; SUN, Tuobei ; PANG, Jian</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO2021238559A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng ; fre</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LAI, Yuanting</creatorcontrib><creatorcontrib>SUN, Tuobei</creatorcontrib><creatorcontrib>PANG, Jian</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LAI, Yuanting</au><au>SUN, Tuobei</au><au>PANG, Jian</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CHIP PACKAGE STRUCTURE AND ELECTRONIC DEVICE</title><date>2021-12-02</date><risdate>2021</risdate><abstract>Provided in the present disclosure are a chip package structure and an electronic device, which belong to the technical field of semiconductor chip package tests. The chip package structure comprises: a package substrate, the package substrate having a first surface and a second surface which are disposed opposite each other; at least one chip, the chip being disposed inside the package substrate, and the chip having a third surface and a fourth surface disposed opposite each other, wherein the third surface is provided with a chip pin; and a heat dissipation structure, the heat dissipation structure being disposed inside the package substrate and located on the fourth surface of the chip, and the side surface of the heat dissipation structure away from the chip is exposed on the second surface of the package substrate, and the heat dissipation structure being used for providing a heat dissipation channel for the chip. FIG. 1
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | CHIP PACKAGE STRUCTURE AND ELECTRONIC DEVICE |
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