COPROCESSORS WITH BYPASS OPTIMIZATION, VARIABLE GRID ARCHITECTURE, AND FUSED VECTOR OPERATIONS

In an embodiment, a coprocessor may include a bypass indication which identifies execution circuitry that is not used by a given processor instruction, and thus may be bypassed. The corresponding circuitry may be disabled during execution, preventing evaluation when the output of the circuitry will...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	BALASUBRAMANIAN, Srikanth, KESIRAJU, Aditya, ALVAREZ-HEREDIA, Boris S, BEAUMONT-SMITH, Andrew J, KANAPATHIPILLAI, Pradeep, CHACHICK, Ran A
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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