STRUCTURE, METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR ELEMENT, AND ELECTRONIC CIRCUIT
This structure includes: a metal oxide semiconductor layer; and a noble metal oxide layer, wherein the metal oxide semiconductor layer and the noble metal oxide layer are adjacent to each other, and the film thickness of the noble metal oxide layer is over 10 nm. La présente invention concerne une s...
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| creator | UEOKA, Yoshihiro NAGASAKI, Yoshikazu KAWASHIMA, Emi TSURUMA, Yuki SEKIYA, Takashi |
| description | This structure includes: a metal oxide semiconductor layer; and a noble metal oxide layer, wherein the metal oxide semiconductor layer and the noble metal oxide layer are adjacent to each other, and the film thickness of the noble metal oxide layer is over 10 nm.
La présente invention concerne une structure comprenant : une couche semi-conductrice d'oxyde métallique ; et une couche d'oxyde de métal noble, la couche semi-conductrice d'oxyde métallique et la couche d'oxyde de métal noble étant adjacentes l'une à l'autre, et l'épaisseur de film de la couche d'oxyde de métal noble étant supérieure à 10 nm.
金属酸化物半導体層と、貴金属酸化物層と、を含み、前記金属酸化物半導体層及び前記貴金属酸化物層は隣接し、前記貴金属酸化物層の膜厚が１０ｎｍ超である構造物。 |
| format | Patent |
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La présente invention concerne une structure comprenant : une couche semi-conductrice d'oxyde métallique ; et une couche d'oxyde de métal noble, la couche semi-conductrice d'oxyde métallique et la couche d'oxyde de métal noble étant adjacentes l'une à l'autre, et l'épaisseur de film de la couche d'oxyde de métal noble étant supérieure à 10 nm.
金属酸化物半導体層と、貴金属酸化物層と、を含み、前記金属酸化物半導体層及び前記貴金属酸化物層は隣接し、前記貴金属酸化物層の膜厚が１０ｎｍ超である構造物。</description><language>eng ; fre ; jpn</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180419&DB=EPODOC&CC=WO&NR=2018070417A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180419&DB=EPODOC&CC=WO&NR=2018070417A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>UEOKA, Yoshihiro</creatorcontrib><creatorcontrib>NAGASAKI, Yoshikazu</creatorcontrib><creatorcontrib>KAWASHIMA, Emi</creatorcontrib><creatorcontrib>TSURUMA, Yuki</creatorcontrib><creatorcontrib>SEKIYA, Takashi</creatorcontrib><title>STRUCTURE, METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR ELEMENT, AND ELECTRONIC CIRCUIT</title><description>This structure includes: a metal oxide semiconductor layer; and a noble metal oxide layer, wherein the metal oxide semiconductor layer and the noble metal oxide layer are adjacent to each other, and the film thickness of the noble metal oxide layer is over 10 nm.
La présente invention concerne une structure comprenant : une couche semi-conductrice d'oxyde métallique ; et une couche d'oxyde de métal noble, la couche semi-conductrice d'oxyde métallique et la couche d'oxyde de métal noble étant adjacentes l'une à l'autre, et l'épaisseur de film de la couche d'oxyde de métal noble étant supérieure à 10 nm.
金属酸化物半導体層と、貴金属酸化物層と、を含み、前記金属酸化物半導体層及び前記貴金属酸化物層は隣接し、前記貴金属酸化物層の膜厚が１０ｎｍ超である構造物。</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAgPDgkKdQ4JDXLVUfB1DfHwd1Fw8w9S8HX0C3VzBIl7-rkrBDv6AqWDXX09nf39XIDKgSpcfVx9Xf1CdBQc_VxAHOeQIH8_T2cFZ88g51DPEB4G1rTEnOJUXijNzaDs5hri7KGbWpAfn1pckJicmpdaEh_ub2RgaGFgbmBiaO5oaEycKgCXzDH4</recordid><startdate>20180419</startdate><enddate>20180419</enddate><creator>UEOKA, Yoshihiro</creator><creator>NAGASAKI, Yoshikazu</creator><creator>KAWASHIMA, Emi</creator><creator>TSURUMA, Yuki</creator><creator>SEKIYA, Takashi</creator><scope>EVB</scope></search><sort><creationdate>20180419</creationdate><title>STRUCTURE, METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR ELEMENT, AND ELECTRONIC CIRCUIT</title><author>UEOKA, Yoshihiro ; NAGASAKI, Yoshikazu ; KAWASHIMA, Emi ; TSURUMA, Yuki ; SEKIYA, Takashi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO2018070417A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; jpn</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>UEOKA, Yoshihiro</creatorcontrib><creatorcontrib>NAGASAKI, Yoshikazu</creatorcontrib><creatorcontrib>KAWASHIMA, Emi</creatorcontrib><creatorcontrib>TSURUMA, Yuki</creatorcontrib><creatorcontrib>SEKIYA, Takashi</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>UEOKA, Yoshihiro</au><au>NAGASAKI, Yoshikazu</au><au>KAWASHIMA, Emi</au><au>TSURUMA, Yuki</au><au>SEKIYA, Takashi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>STRUCTURE, METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR ELEMENT, AND ELECTRONIC CIRCUIT</title><date>2018-04-19</date><risdate>2018</risdate><abstract>This structure includes: a metal oxide semiconductor layer; and a noble metal oxide layer, wherein the metal oxide semiconductor layer and the noble metal oxide layer are adjacent to each other, and the film thickness of the noble metal oxide layer is over 10 nm.
La présente invention concerne une structure comprenant : une couche semi-conductrice d'oxyde métallique ; et une couche d'oxyde de métal noble, la couche semi-conductrice d'oxyde métallique et la couche d'oxyde de métal noble étant adjacentes l'une à l'autre, et l'épaisseur de film de la couche d'oxyde de métal noble étant supérieure à 10 nm.
金属酸化物半導体層と、貴金属酸化物層と、を含み、前記金属酸化物半導体層及び前記貴金属酸化物層は隣接し、前記貴金属酸化物層の膜厚が１０ｎｍ超である構造物。</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | STRUCTURE, METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR ELEMENT, AND ELECTRONIC CIRCUIT |
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