PIPELINED PREFETCHER FOR PARALLEL ADVANCEMENT OF MULTIPLE DATA STREAMS

A processor includes a front end to decode instructions, an execution unit to execute instructions, multiple caches at different cache hierarchy levels, a pipelined prefetcher, and a retirement unit to retire instructions. The prefetcher includes circuitry to receive a demand request for data at a f...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	NUZMAN, Joseph, PELED, Leeor, NOVAKOVSKY, Larisa
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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