MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE

Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ("LLC"), and a har...

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Hauptverfasser:	MA, Te K, VANGATI, Narender, VAN DOREN, Stephen R, BURRES, Bradley A, WANG, Ren, MCDONNELL, Niall D, SONNIER, David, BERNSTEIN, Debra, WANG, Yipeng, VENKATESAN, Namakkal N, VERPLANKE, Edwin, CUNNINGHAM, Andrew, EADS, Gage, YAN, An, TSAI, Jr-Shian, CLEE, James T, HERDRICH, Andrew J, WHITESELL, Jamison D, KENNY, Jonathan, TAI, Tsung-Yuan C, MILLER, Stephen, WILKINSON, Hugh, BURROUGHS, William, RICHARDSON, Bruce, HASTING, Joseph R, PIROG, Jerry
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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