COMPLEX LAYOUT-BASED TOPOLOGICAL DATA ANALYSIS OF ANALOG NETLISTS TO EXTRACT HIERARCHY AND FUNCTIONALITY
A system and method for reverse synthesizing an integrated circuit from a netlist. A netlist extracted from a device under review is received and converted to a connected graph. Blocks of cells are identified within the connected graph and a circuit model is formed from the blocks of cells, wherein...
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| creator | REDEKOPP, MARK W SAGHIZADEH, PARVIZ SPARGO, THOMAS ALLEN NARUMI, ROBERT T |
| description | A system and method for reverse synthesizing an integrated circuit from a netlist. A netlist extracted from a device under review is received and converted to a connected graph. Blocks of cells are identified within the connected graph and a circuit model is formed from the blocks of cells, wherein forming includes iteratively building more complex blocks of cells from simpler blocks of cells.
L'invention concerne un système et un procédé pour une synthèse inverse d'un circuit intégré à partir d'une liste d'interconnexions. Une liste d'interconnexions extraite à partir d'un dispositif en cours de révision est reçue et convertie en un graphique connecté. Des blocs de cellules sont identifiés dans le graphique connecté et un modèle de circuit est formé à partir des blocs de cellules, la formation comprenant la construction de manière itérative de blocs de cellules plus complexes à partir de blocs de cellules plus simples. |
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L'invention concerne un système et un procédé pour une synthèse inverse d'un circuit intégré à partir d'une liste d'interconnexions. Une liste d'interconnexions extraite à partir d'un dispositif en cours de révision est reçue et convertie en un graphique connecté. Des blocs de cellules sont identifiés dans le graphique connecté et un modèle de circuit est formé à partir des blocs de cellules, la formation comprenant la construction de manière itérative de blocs de cellules plus complexes à partir de blocs de cellules plus simples.</description><language>eng ; fre</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150820&DB=EPODOC&CC=WO&NR=2015053852A9$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150820&DB=EPODOC&CC=WO&NR=2015053852A9$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>REDEKOPP, MARK W</creatorcontrib><creatorcontrib>SAGHIZADEH, PARVIZ</creatorcontrib><creatorcontrib>SPARGO, THOMAS ALLEN</creatorcontrib><creatorcontrib>NARUMI, ROBERT T</creatorcontrib><title>COMPLEX LAYOUT-BASED TOPOLOGICAL DATA ANALYSIS OF ANALOG NETLISTS TO EXTRACT HIERARCHY AND FUNCTIONALITY</title><description>A system and method for reverse synthesizing an integrated circuit from a netlist. A netlist extracted from a device under review is received and converted to a connected graph. Blocks of cells are identified within the connected graph and a circuit model is formed from the blocks of cells, wherein forming includes iteratively building more complex blocks of cells from simpler blocks of cells.
L'invention concerne un système et un procédé pour une synthèse inverse d'un circuit intégré à partir d'une liste d'interconnexions. Une liste d'interconnexions extraite à partir d'un dispositif en cours de révision est reçue et convertie en un graphique connecté. Des blocs de cellules sont identifiés dans le graphique connecté et un modèle de circuit est formé à partir des blocs de cellules, la formation comprenant la construction de manière itérative de blocs de cellules plus complexes à partir de blocs de cellules plus simples.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNysEKgkAQgGEvHaJ6h4HOgilCHqfdVRc2R9yR3JNIbHSIEuz9aYkeoNP_H751dBd0bo0awKCjnuMTWiWBqSVDlRZoQCIjYIPGWW2Byu9TBY1ioy3bgEEN3KFgqLXqsBO1C0hC2TeCNQWu2W2j1W16LH736ybal4pFHfv5Nfplnq7-6d_jhdLkkCd5dsxTLLL_1AcdSTbg</recordid><startdate>20150820</startdate><enddate>20150820</enddate><creator>REDEKOPP, MARK W</creator><creator>SAGHIZADEH, PARVIZ</creator><creator>SPARGO, THOMAS ALLEN</creator><creator>NARUMI, ROBERT T</creator><scope>EVB</scope></search><sort><creationdate>20150820</creationdate><title>COMPLEX LAYOUT-BASED TOPOLOGICAL DATA ANALYSIS OF ANALOG NETLISTS TO EXTRACT HIERARCHY AND FUNCTIONALITY</title><author>REDEKOPP, MARK W ; SAGHIZADEH, PARVIZ ; SPARGO, THOMAS ALLEN ; NARUMI, ROBERT T</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO2015053852A93</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>2015</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>REDEKOPP, MARK W</creatorcontrib><creatorcontrib>SAGHIZADEH, PARVIZ</creatorcontrib><creatorcontrib>SPARGO, THOMAS ALLEN</creatorcontrib><creatorcontrib>NARUMI, ROBERT T</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>REDEKOPP, MARK W</au><au>SAGHIZADEH, PARVIZ</au><au>SPARGO, THOMAS ALLEN</au><au>NARUMI, ROBERT T</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>COMPLEX LAYOUT-BASED TOPOLOGICAL DATA ANALYSIS OF ANALOG NETLISTS TO EXTRACT HIERARCHY AND FUNCTIONALITY</title><date>2015-08-20</date><risdate>2015</risdate><abstract>A system and method for reverse synthesizing an integrated circuit from a netlist. A netlist extracted from a device under review is received and converted to a connected graph. Blocks of cells are identified within the connected graph and a circuit model is formed from the blocks of cells, wherein forming includes iteratively building more complex blocks of cells from simpler blocks of cells.
L'invention concerne un système et un procédé pour une synthèse inverse d'un circuit intégré à partir d'une liste d'interconnexions. Une liste d'interconnexions extraite à partir d'un dispositif en cours de révision est reçue et convertie en un graphique connecté. Des blocs de cellules sont identifiés dans le graphique connecté et un modèle de circuit est formé à partir des blocs de cellules, la formation comprenant la construction de manière itérative de blocs de cellules plus complexes à partir de blocs de cellules plus simples.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | COMPLEX LAYOUT-BASED TOPOLOGICAL DATA ANALYSIS OF ANALOG NETLISTS TO EXTRACT HIERARCHY AND FUNCTIONALITY |
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