METHOD AND APPARATUS FOR CONDUCTING AUTOMATED INTEGRATED CIRCUIT ANALYSIS
A method and apparatus for scanning an integrated circuit comprising a plurality of time-synchronized laser microscopes, each of which is configured to scan the same field of view of an integrated circuit under test that generates a plurality of images of the integrated circuit under test, a data pr...
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| creator | AGRAWAL, MOTILAL STOKER, DAVID S TROY, NEIL WILLIAM POTTHAST, JAMES R MATLIN, ERIK FRANK |
| description | A method and apparatus for scanning an integrated circuit comprising a plurality of time-synchronized laser microscopes, each of which is configured to scan the same field of view of an integrated circuit under test that generates a plurality of images of the integrated circuit under test, a data processor, coupled to the laser scanning microscope, for processing the plurality of images, comprising, a netlist extractor (NE) that produces one or more netlists defining structure of the integrated circuit under test.
Procédé et appareil destinés à balayer un circuit intégré, ledit appareil comprenant une pluralité de microscopes laser à synchronisation temporelle, dont chacun est configuré pour balayer le même champ de vision d'un circuit intégré testé et génère une pluralité d'images du circuit intégré testé, et un processeur de données couplé au microscope à balayage laser, pour le traitement de la pluralité d'images, qui comporte un extracteur de liste d'interconnexions (NE) produisant une ou plusieurs listes d'interconnexions définissant la structure du circuit intégré testé. |
| format | Patent |
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Procédé et appareil destinés à balayer un circuit intégré, ledit appareil comprenant une pluralité de microscopes laser à synchronisation temporelle, dont chacun est configuré pour balayer le même champ de vision d'un circuit intégré testé et génère une pluralité d'images du circuit intégré testé, et un processeur de données couplé au microscope à balayage laser, pour le traitement de la pluralité d'images, qui comporte un extracteur de liste d'interconnexions (NE) produisant une ou plusieurs listes d'interconnexions définissant la structure du circuit intégré testé.</description><language>eng ; fre</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140703&DB=EPODOC&CC=WO&NR=2014105304A2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140703&DB=EPODOC&CC=WO&NR=2014105304A2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>AGRAWAL, MOTILAL</creatorcontrib><creatorcontrib>STOKER, DAVID S</creatorcontrib><creatorcontrib>TROY, NEIL WILLIAM</creatorcontrib><creatorcontrib>POTTHAST, JAMES R</creatorcontrib><creatorcontrib>MATLIN, ERIK FRANK</creatorcontrib><title>METHOD AND APPARATUS FOR CONDUCTING AUTOMATED INTEGRATED CIRCUIT ANALYSIS</title><description>A method and apparatus for scanning an integrated circuit comprising a plurality of time-synchronized laser microscopes, each of which is configured to scan the same field of view of an integrated circuit under test that generates a plurality of images of the integrated circuit under test, a data processor, coupled to the laser scanning microscope, for processing the plurality of images, comprising, a netlist extractor (NE) that produces one or more netlists defining structure of the integrated circuit under test.
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Procédé et appareil destinés à balayer un circuit intégré, ledit appareil comprenant une pluralité de microscopes laser à synchronisation temporelle, dont chacun est configuré pour balayer le même champ de vision d'un circuit intégré testé et génère une pluralité d'images du circuit intégré testé, et un processeur de données couplé au microscope à balayage laser, pour le traitement de la pluralité d'images, qui comporte un extracteur de liste d'interconnexions (NE) produisant une ou plusieurs listes d'interconnexions définissant la structure du circuit intégré testé.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING |
| title | METHOD AND APPARATUS FOR CONDUCTING AUTOMATED INTEGRATED CIRCUIT ANALYSIS |
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