BUILT IN SELF-TESTING AND REPAIR DEVICE AND METHOD

A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the...

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Hauptverfasser: KLEVELAND, BENDIK, PATEL, JAY, SIKDAR, DIPAK, K, CHOPRA, RAJESH
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creator KLEVELAND, BENDIK
PATEL, JAY
SIKDAR, DIPAK, K
CHOPRA, RAJESH
description A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks. La présente invention concerne un dispositif à mémoire à autotest intégré d'arrière-plan (BBIST) comprenant une pluralité de blocs mémoires ; une mémoire tampon servant à décharger temporairement des données de l'un de la pluralité de blocs mémoires ; et un dispositif de commande de contrainte de blocs mémoires servant à commander un test de contrainte appliqué à l'un des blocs mémoires lorsque les données sont temporairement déchargées sur la mémoire tampon. Le test de contrainte effectue un test d'erreurs dans l'un de la pluralité de blocs mémoires.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_WO2013102230A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>WO2013102230A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_WO2013102230A13</originalsourceid><addsrcrecordid>eNrjZDByCvX0CVHw9FMIdvVx0w1xDQ7x9HNXcPRzUQhyDXD0DFJwcQ3zdHYFi_i6hnj4u_AwsKYl5hSn8kJpbgZlN9cQZw_d1IL8-NTigsTk1LzUkvhwfyMDQ2NDAyMjYwNHQ2PiVAEA31AnKw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>BUILT IN SELF-TESTING AND REPAIR DEVICE AND METHOD</title><source>esp@cenet</source><creator>KLEVELAND, BENDIK ; PATEL, JAY ; SIKDAR, DIPAK, K ; CHOPRA, RAJESH</creator><creatorcontrib>KLEVELAND, BENDIK ; PATEL, JAY ; SIKDAR, DIPAK, K ; CHOPRA, RAJESH</creatorcontrib><description>A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks. La présente invention concerne un dispositif à mémoire à autotest intégré d'arrière-plan (BBIST) comprenant une pluralité de blocs mémoires ; une mémoire tampon servant à décharger temporairement des données de l'un de la pluralité de blocs mémoires ; et un dispositif de commande de contrainte de blocs mémoires servant à commander un test de contrainte appliqué à l'un des blocs mémoires lorsque les données sont temporairement déchargées sur la mémoire tampon. Le test de contrainte effectue un test d'erreurs dans l'un de la pluralité de blocs mémoires.</description><language>eng ; fre</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130704&amp;DB=EPODOC&amp;CC=WO&amp;NR=2013102230A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130704&amp;DB=EPODOC&amp;CC=WO&amp;NR=2013102230A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KLEVELAND, BENDIK</creatorcontrib><creatorcontrib>PATEL, JAY</creatorcontrib><creatorcontrib>SIKDAR, DIPAK, K</creatorcontrib><creatorcontrib>CHOPRA, RAJESH</creatorcontrib><title>BUILT IN SELF-TESTING AND REPAIR DEVICE AND METHOD</title><description>A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks. La présente invention concerne un dispositif à mémoire à autotest intégré d'arrière-plan (BBIST) comprenant une pluralité de blocs mémoires ; une mémoire tampon servant à décharger temporairement des données de l'un de la pluralité de blocs mémoires ; et un dispositif de commande de contrainte de blocs mémoires servant à commander un test de contrainte appliqué à l'un des blocs mémoires lorsque les données sont temporairement déchargées sur la mémoire tampon. Le test de contrainte effectue un test d'erreurs dans l'un de la pluralité de blocs mémoires.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDByCvX0CVHw9FMIdvVx0w1xDQ7x9HNXcPRzUQhyDXD0DFJwcQ3zdHYFi_i6hnj4u_AwsKYl5hSn8kJpbgZlN9cQZw_d1IL8-NTigsTk1LzUkvhwfyMDQ2NDAyMjYwNHQ2PiVAEA31AnKw</recordid><startdate>20130704</startdate><enddate>20130704</enddate><creator>KLEVELAND, BENDIK</creator><creator>PATEL, JAY</creator><creator>SIKDAR, DIPAK, K</creator><creator>CHOPRA, RAJESH</creator><scope>EVB</scope></search><sort><creationdate>20130704</creationdate><title>BUILT IN SELF-TESTING AND REPAIR DEVICE AND METHOD</title><author>KLEVELAND, BENDIK ; PATEL, JAY ; SIKDAR, DIPAK, K ; CHOPRA, RAJESH</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_WO2013102230A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>2013</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>KLEVELAND, BENDIK</creatorcontrib><creatorcontrib>PATEL, JAY</creatorcontrib><creatorcontrib>SIKDAR, DIPAK, K</creatorcontrib><creatorcontrib>CHOPRA, RAJESH</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KLEVELAND, BENDIK</au><au>PATEL, JAY</au><au>SIKDAR, DIPAK, K</au><au>CHOPRA, RAJESH</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>BUILT IN SELF-TESTING AND REPAIR DEVICE AND METHOD</title><date>2013-07-04</date><risdate>2013</risdate><abstract>A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks. La présente invention concerne un dispositif à mémoire à autotest intégré d'arrière-plan (BBIST) comprenant une pluralité de blocs mémoires ; une mémoire tampon servant à décharger temporairement des données de l'un de la pluralité de blocs mémoires ; et un dispositif de commande de contrainte de blocs mémoires servant à commander un test de contrainte appliqué à l'un des blocs mémoires lorsque les données sont temporairement déchargées sur la mémoire tampon. Le test de contrainte effectue un test d'erreurs dans l'un de la pluralité de blocs mémoires.</abstract><oa>free_for_read</oa></addata></record>
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STATIC STORES
title BUILT IN SELF-TESTING AND REPAIR DEVICE AND METHOD
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T13%3A00%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KLEVELAND,%20BENDIK&rft.date=2013-07-04&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EWO2013102230A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true